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One question regarding INT registers clearing for edge triggering

Rui Zhang69778
Genius 4525 points

For edge trigger INT, I believe we should clear CPU interrupt flag registers prior to clearing source flag bit, otherwise we may miss interrupt? I don't understand why we may miss interrupt if we clear source flag before CPU flag, since CPU flag is there, we will eventually execute the INT anyway, right?

Thanks

Rui

  • 0
    Guru 22270 points

    Hello Rui,

    I think you just have to follow the logic of the interrupt processing.  The CPU flag is set regardless of whether or not an interrupt is enabled and then it vectors to the appropriate routine that is enabled.  If you clear the source flag first and another interrupt occurs while the CPU is processing another interrupt of equal or higher priority, the CPU will only service to second interrupt.  The first interrupt would be lost.

    Clearing the CPU interrupt flag ensures that any new interrupt will be now become pending.

    At least that is my interpretation of it.  When using slower 8051 MCUs and simulators where you can see that the interrupts are missed because the CPU was in the process of responding to another interrupt.

  • 0 in reply to Greenja
    Genius 4525 points

    Thanks, but I am still a little bit confused.

    supposing you got a P0 INT, then  the bit 5 of IRCON CPU interrupt flag is set, then before you serve the P0 int vector, another DMA int arrives,bit 0 of IRCON CPU interrupt flag is set. SW process the DMA first and clear the IRCON bit 0, after ISR_DMA finished, you still have IRCON bit 5 set and can process P0 interrupt, so no interrupt is missing.

    Where am I wrong?

    Thanks

    Rui

  • 0 in reply to Rui Zhang69778
    Guru 22270 points

    I believe the problem arises when you are dealing with the same interrupt bit.  If you were only dealing with bit 5 and you clear the flag before you clear the CPU flag, then if another interrupt happens on bit 5 lets say within 7 cycles or so, the CPU will not add it to the call stack.  It will appear to be the interrupt it had originally started vectoring to.

    The best way to see it would be on any of the simulators for the 8051.  There are about 100 000 of them out there.  Write a small routine with interrupts and then toggle the port bits.  IAR should be able to do it, but I find using it to troubleshoot difficult.  You will see how the CPU behaves and you will also notice that if you toggle within a certain period, nothing is added to the call stack.  Hence, the interrupt is missed.

    Perhaps someone from TI could better explain it, or you could do a search on the web for how the 8051 handles interrupts.  There is a 80C51 family hardware description, 80C51family architecture by Philips out there that details interrupt routines more thoroughly.

  • 0 in reply to Greenja
    TI__Genius 10955 points

    The explanation by greenja is correct. Please note that your example of P0INT is not an example of an edge triggered interrupt seen by the 8051 (this is explained in this thread: http://e2e.ti.com/support/low_power_rf/f/158/p/148316/537073.aspx). Also, as greenja explains, the problem is not when dealing with two different interrupt vectors, but several interrupts on the same vector.