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CC2538: Strange behavior of SPI "Slave" ISR

Pavel Yermolenko
Intellectual 660 points
Other Parts Discussed in Thread: CC2538

Hello,

Here is my setup:

PC (with FTDI bridge) - SPI "Master"

CC2538 - SPI "Slave"

Here is the problem:

In spite of the fact that only RX FIFO time-out interrupt were enabled, the "Slave" ISR is armed not only during reception ("Master" writes "Slave"), but also during transmission ("Master" reads "Slave").

Did someone met the same problem ?


Thanks in advance.


Pavel

  • 0
    TI__Mastermind 35795 points

    Pavel,

    This is normal SPI full-duplex mode, which means SPI can transmit and receive at the same time.

    Saurabh

  • 0 in reply to S
    Intellectual 660 points

    Hello Saurabh,

    Thank you for feedback.

    Can I desactivate full-duplex ?

    I want ISR being armed only when "Master" writes "Slave". Is it possible ?

    BR

    Pavel

  • 0 in reply to Pavel Yermolenko
    TI__Genius 9180 points

    I do not think it is not possible to configure the SPI module for half duplex operation.

    Typically a protocol on top of SPI is used to over come synchronization issues and TX and RX are run full duplex independently. Framing (start of frame and lengths bytes) can be used to insure all bytes are received, the master must manage clocking in/out all bits.

    However If you want to implement half duplex in SW you can do the following in "TX mode":

    Disable the RX interrupt in the SSI_IM RXIM, RTIM and RORIM, enable TXIM. Tx data.

    In RX mode:

    read Tx bytes from RX FIFO (clock in during TX mode) enable the RX interrupt in the SSI_IM RXIM, RTIM and RORIM, disable TXIM. Rx data.

    However you will then have some Sync issue, when does slave / master know when each other are in Tx/Rx mode? you could use GPIO's to indicate when ready for Rx. 

    Regards, TC.

  • 0 in reply to TopCat
    Intellectual 660 points

    Hello TopCat,

    Thanks for feedback.

    If I properly undrestood your scenario, once device is powered, none interrupt is activated.

    If it's the case such setup won't work, as it is the MASTER (PC in my case), that initiate exchange.

    Regards

    Pavel

  • 0 in reply to Pavel Yermolenko
    TI__Genius 9180 points

    It should be possible. I am not familiar with the SPI FTDI driver for windows, but it is likely half duplex with a write function and a read function.

    So you could implement in SW a mechanism where the the CC2538 is always ready to receive data. The pc wraps the data it wants to send in a start of frame byte (0xFE) followed by a Len byte/word. So the when the host wants to send 4 bytes (0x01, 0x02, 0x03, 0x04), it sends:

    SOF    |    LEN    |                    DATA

    0xFE        0x04        0x01, 0x02, 0x03, 0x04

    The CC2538 knows to "listen" for a 0xFE, read a length byte and expect <length> bytes of data, and ignore any other data clocked in, which may be due to a read (it is full duplex so it will clock in data even when the host is reading the data being clocked out).

    When the host wants to read data from the CC2538 it can do something like send a 0 length write (or maybe a different SOF) to inform the CC2538 it is about to do a read, waits an arbitrary amount of time for the CC2538 to set it up, then clock in 2 bytes, it will expect to see from the CC2538:

    SOF    |    LEN    |

    0xFE        0x0A

    In this case the CC2538 has 10 (0x0A) bytes to send, the host then knows to read 10 bytes.

    Regards, TC.  

     

  • 0 in reply to TopCat
    Intellectual 660 points

    It was good idea.

    Now it works much better. Thanks !!!