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LPRF design on 4 layers

AlvJorge
Intellectual 575 points

Developing a new design on a 4-layer stack with reduced dimensions, there are some doubts I expect you can help me with.

  • The board includes RF part, MCU, voltage regulator & battery charger.
  • Power comes from an USB connector, then space need to be shared out not only with components as well as with power and signal lines.
  • To avoid routing high current traces into inner layer, and make split planes, the idea is to maintain the high current power lines (VBUS, VBAT) into TOP layer. Routing to inner layer the low current power traces (VDD) and the signal ones.

 For such design, two options are being considered.

  1. TOP: components + high current PWR lines + signals; L2: GND plane; L3: PWR plane (VDD only); BOTTOM: GND + signals.
    1. The doubt here is the differential pairs (clk, I2C, USB). Will the performance be affected in case of routing this kind of signals from TOP layer to BOTTOM & viceversa to not cross them with PWR traces?
TOP: components + high current PWR lines + signals; L2: GND plane; L3: GND plane + PWR (VDD only) + signals; BOTTOM: GND plane.
  1. Doing at this manner, will the noise be increased? Will the differential pairs be affected (although they are shielded between GND traces/planes)?

Are one of previous questions suitable to accomplish the guidelines? Or there is another better option?

Kind Regards.

  • 0
    TI__Mastermind 36395 points

    Jorge,

    It is hard to answer these types of speculative questions without being able to see a representative layout.

    But in general I see no issues running higher power traces on the top surface.

    When you say high power, how much are you refering to?

    From your list of questions, you wrote that you intend to place a power plane on layer 3. I do not recommend using power planes for mixed signal circuit boards containing RF signals. The main reason is that RF signals will find a way to couple onto the power plane it will then either find a different circuit to attack or it will radiate out the perimeter of the PCB and you will trouble pass radiated emissions requirements.

    Regards,

    /TTA

  • 0 in reply to TA12012
    Intellectual 575 points
    Hi TA12012,

    Thanks!

    Yes, questions are not pretty specific. But, I need a second opinion in how implement the design, because at top layer, with components, there is no much free space to route, so I need to use another layer for routing power and signals traces.

    With high current I'm talking about 1.5A DC. Perphaps, I oversized the case, but taking into account that design has reduced dimensions, the space needed is important for (VBUS) power traces. I'm trying to not increase the board dimensions too much.

    My main worry is about mix in the same layer digital&clock signals with power lines, even when power lines are low power ones.

    Regards.