I changed SampleSwitch project in zstack_home_1_02_02a_44539 from IAR to CCS and complete building project.
Now I try to run SampleSwitch project on SmartRF06 Board with CC2650-7ID using CCSv6.
I think that my problem is semaphore.
After BIOS_start() in main.c, Switch task is not working.
I change SampleSwitch project little.
Void main()
{
//Task_Params taskParams;
// set RFC mode to support IEEE802.15.4
// Note: This must be done before the RF Core is released from reset!
SET_RFC_MODE(RFC_MODE_IEEE);
/* Initialization for board related stuff such as LEDs
* following TI-RTOS convention */
PIN_init(BoardGpioInitTable);
// enable iCache prefetching
VIMSConfigure(VIMS_BASE, TRUE, TRUE);
// Enable cache
VIMSModeSet(VIMS_BASE, VIMS_MODE_ENABLED);
// // Configure task.
// Task_Params_init(&taskParams);
// taskParams.stack = myTaskStack;
// taskParams.stackSize = MY_TASK_STACK_SIZE;
// taskParams.priority = 1;
// Task_construct(&myTask, taskFxn, &taskParams, NULL);
/* Disallow shutting down JTAG, VIMS, SYSBUS during idle state
* since TIMAC requires SYSBUS during idle. */
Power_setConstraint(Power_IDLE_PD_DISALLOW);
/* Initialize the Power Monitor */
PWRMON_init();
/* Initialize ICall module */
ICall_init();
{
CryptoCC26XX_Params CryptoCC26XXParams;
extern CryptoCC26XX_Handle CryptoCC26XXHandle;
// Initialize the Crypto Driver
CryptoCC26XX_init();
CryptoCC26XX_Params_init(&CryptoCC26XXParams);
CryptoCC26XXHandle = CryptoCC26XX_open(Board_CRYPTO, false,
&CryptoCC26XXParams);
if(!CryptoCC26XXHandle)
{
Task_exit();
}
Crypto_init();
}
/*
* Copy the extended address from the CCFG area
* Assumption: the memory in CCFG_IEEE_MAC_0 and CCFG_IEEE_MAC_1
* is contiguous and LSB first.
*/
memcpy(user0Cfg.extendedAddress,
(uint8_t *)&(__ccfg.CCFG_IEEE_MAC_0), EXTADDR_LEN);
// Check to see if the CCFG IEEE is valid
if(memcmp(user0Cfg.extendedAddress, dummyExtAddr, EXTADDR_LEN) == 0)
{
// No, it isn't valid. Get the Primary IEEE Address
memcpy(user0Cfg.extendedAddress,
(uint8_t *)(FCFG1_BASE + EXTADDR_OFFSET), EXTADDR_LEN);
}
// Make sure the voltage level is high enough to operate
while ( PWRMON_check( MIN_VDD_RUN ) == false )
{
// Add your own code to do something here, flash LED, sleep, something
// For now, we will loop and wait for power comes up to the
// MIN_VDD_RUN level.
}
#if !defined (FEATURE_APP_NO_NV_INIT)
/* Setup the NV driver for the ZStack thread */
NVOCTP_loadApiPtrs(&user0Cfg.nvFps);
#endif // !FEATURE_APP_NO_NV_INIT
if(user0Cfg.nvFps.initNV)
{
user0Cfg.nvFps.initNV(NULL);
}
/* Start tasks of external images */
ICall_createRemoteTasks();
/* Kick off application */
Switch_task(&user0Cfg.nvFps);
BIOS_start(); /* enable interrupts and start SYS/BIOS */
}
The task create code is original code.
The code under task create (Power_setConstraint ()~ Switch_task()) was in taskFxn() and is now in main().
Look at the picture.
After BIOS_start(), I push the suspend button.
ICall_taskEntry is running. So, Other tasks is not running because the semaphore in switch and icall tasks are not working.
And this picture is semaphore at ROV. 2nd and 3rd semaphore is not pended by switch and icall tasks.
I add the ccs files (except for app.cfg) on the existing example projects such as SimpleBLECentral project.
I adjust STACK and RAM address to coreEndDevice files, but the configuration file is changed.
And I attach the CCS configuration files and the list of file is below with my reference IAR configuration file.
<CCS files>
- ccsCompilerDefines.bcfg
/* WARNING - Do not modify this line. Modifications below this line can be overwritten by the Boundary tool */ /* Boundary auto gen parser version 1.0.3 */ /* CCS Compiler Command Line Options */ /* Auto-generated compiler option(s) */ --define=ICALL_STACK0_ADDR=0x0000A000
- ccsLinkerDefines.cmd
/* WARNING - Do not modify this line. Modifications below this line can be overwritten by the Boundary tool */ /* Boundary auto gen parser version 1.0.3 */ /* CCS Linker Command Line Options */ /* Auto-generated linker option(s) */ --define=ICALL_STACK0_ADDR=0x0000A000 --define=ICALL_RAM0_ADDR=0x200042C8
- app.cfg
/* sysbios */
var useSysbiosInRom = true;
if ( useSysbiosInRom )
{
var ROM = xdc.useModule('ti.sysbios.rom.ROM');
ROM.romName = ROM.CC2650;
}
var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Types = xdc.useModule('xdc.runtime.Types');
var Diags = xdc.useModule('xdc.runtime.Diags');
var Error = xdc.useModule('xdc.runtime.Error');
var Main = xdc.useModule('xdc.runtime.Main');
var Memory = xdc.useModule('xdc.runtime.Memory')
var SysCallback = xdc.useModule('xdc.runtime.SysCallback');
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
if ( useSysbiosInRom )
{
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
}
else
{
var HeapMin = xdc.useModule('xdc.runtime.HeapMin');
}
var Reset = xdc.useModule('xdc.runtime.Reset');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
var Power = xdc.useModule('ti.sysbios.family.arm.cc26xx.Power');
/* Enable idle task (default). */
Task.enableIdleTask = true;
/* Idle CPU when threads blocked waiting for an interrupt */
Power.idle = true;
Power.policyFunc = Power.standbyPolicy;
//Power.calibrateRCOSC = false;
/* compile out all Assert's */
Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
/* Don't load string names of modules on the target */
Defaults.common$.namedModule = false;
/* Allow Mod_create() and Mod_construct() but not delete() or destruct() */
Defaults.common$.memoryPolicy = Types.CREATE_POLICY;
/* Don't load diagnostic/descriptive text strings on the target */
Text.isLoaded = false;
/* Use the minimal user-supplied callback provider */
System.SupportProxy = SysCallback;
/* no exit handlers needed */
System.maxAtexitHandlers = 0;
/* main() and Hwi, Swi stack size */
Program.stack = 512;
if ( useSysbiosInRom )
{
/* no command-line arguments main(argc, argv) needed */
Program.argSize = 0;
}
/* build a custom, optimized version of SYS/BIOS */
BIOS.libType = BIOS.LibType_Custom;
/* no logging - all compiled out */
BIOS.logsEnabled = false;
/* disable Asserts in SYS/BIOS code */
BIOS.assertsEnabled = false;
/* Reduce number of Task priority levels to save RAM */
Task.numPriorities = 6;
/* Set the default Task stack size - used if one is not specified */
Task.defaultStackSize = 512;
/* Don't check stacks for overflow - saves cycles (and power) and Flash */
Task.checkStackFlag = false;
/* Disable exception handling to save Flash - undo during active development */
M3Hwi.enableException = true;
M3Hwi.excHandlerFunc = null; /* null = default while loop function. Use e.g. "&myFxn" to use your own function. */
M3Hwi.nvicCCR.UNALIGN_TRP = 0;
M3Hwi.nvicCCR.DIV_0_TRP = 0;
/* Don't check for interrupt stack overflow during Idle loop */
Hwi.checkStackFlag = false;
/* Minimize Flash and RAM usage of Error module */
Error.raiseHook = null; /* null = default while loop function. Use e.g. "&myFxn" to your own handler function. */
Error.maxDepth = 2;
/* Set the default CPU frequency */
BIOS.cpuFreq.lo = 48000000;
/* Put reset vector at start of Flash */
M3Hwi.resetVectorAddress = 0x0;
/* Put interrupt vector at start of RAM so interrupts can be configured at runtime */
M3Hwi.vectorTableAddress = 0x20000000;
/* CC2650 has 50 interrupts */
M3Hwi.NUM_INTERRUPTS = 50;
if ( useSysbiosInRom )
{
/* Create a small "alloc-only" heap */
BIOS.heapSize = 1924;
}
else
{
var heapMinParams = new HeapMin.Params;
heapMinParams.size = 1924;
var myHeapMin = HeapMin.create(heapMinParams);
Memory.defaultHeapInstance = myHeapMin;
}
var Swi = xdc.useModule('ti.sysbios.knl.Swi');
Swi.numPriorities = 6;
BIOS.swiEnabled = true;
BIOS.includeXdcRuntime = true;
/* Tasks cannot pend based on priority */
Semaphore.supportsPriority = false;
/* Change default error function -- just spin */
Error.policyFxn = Error.policySpin;
/* true: Allow runtime creation of e.g. semaphores
* false: Compile out reference to Memory in BIOS */
BIOS.runtimeCreatesEnabled = true;
/* Abort and exit functions -- just spin */
System.abortFxn = System.abortSpin;
System.exitFxn = System.exitSpin;
/* CC26xx Boot module */
var Boot = xdc.useModule('ti.sysbios.family.arm.cc26xx.Boot');
Boot.driverlibVersion = 2;
Boot.customerConfig = false;
//Boot.checkBackdoor = true;
/* Clock tick Period set to 10 us if not defined */
Clock.tickPeriod = 10;
/* Driver configuration */
var TIRTOS = xdc.useModule('ti.tirtos.TIRTOS');
TIRTOS.useGPIO = true;
/* Disable RCOSC calibration feature to support fast HF crystal startup and LF crystal-less operation */
Power.calibrateRCOSC = false;
- cc26xx_zigbee_app.cmd
/* Retain interrupt vector table variable */
--retain=g_pfnVectors
/* Override default entry point. */
--entry_point ResetISR
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=128 */
/* --library=rtsv7M3_T_le_eabi.lib */
/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define APP_BASE 0x00000000
#define FLASH_SIZE 0x20000
#define RAM_BASE 0x20000000
#define RAM_SIZE 0x5000
#define CCA_NUM_ENTRIES 21
#define CCA_SIZE (CCA_NUM_ENTRIES * 4)
/* System memory map */
MEMORY
{
/* EDITOR'S NOTE:
* the FLASH and SRAM lengths can be changed by defining
* ICALL_STACK0_ADDR or ICALL_RAM0_ADDR in
* Properties->ARM Linker->Advanced Options->Command File Preprocessing.
*/
/* Application stored in and executes from internal flash */
/* Flash Size 128 KB */
#ifdef ICALL_STACK0_ADDR
FLASH (RX) : origin = APP_BASE, length = ICALL_STACK0_ADDR - APP_BASE - 1
#else // default
FLASH (RX) : origin = APP_BASE, length = 0x00008FFF
#endif
// CCFG Page, contains .ccfg code section and some application code.
FLASH_CCA (RX) : origin = FLASH_SIZE - CCA_SIZE, length = CCA_SIZE
/* Application uses internal RAM for data */
/* RAM Size 16 KB */
#ifdef ICALL_RAM0_ADDR
SRAM (RWX) : origin = RAM_BASE, length = ICALL_RAM0_ADDR - RAM_BASE - 1
#else //default
SRAM (RWX) : origin = RAM_BASE, length = 0x000037FF
#endif
}
/* Section allocation in memory */
SECTIONS
{
.intvecs : > APP_BASE
.text : >> FLASH
.const : >> FLASH
.constdata : >> FLASH
.rodata : >> FLASH
.cinit : > FLASH
.pinit : >> FLASH
.init_array : >> FLASH
.emb_text : >> FLASH
.ccfg : > FLASH_CCA (HIGH)
.vtable : > SRAM
.vtable_ram : > SRAM
vtable_ram : > SRAM
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM (HIGH)
.nonretenvar : > SRAM
}
/* Create global constant that points to top of stack */
/* CCS: Change stack size under Project Properties */
__STACK_TOP = __stack + __STACK_SIZE;
/* Allow main() to take args */
--args 0x8
- cc26xx_zigbee_stack.cmd
/* Retain interrupt vector table variable */
--retain=g_pfnVectors
/* Override default entry point. */
//--entry_point ResetISR
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=128 */
/* --library=rtsv7M3_T_le_eabi.lib */
/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define APP_BASE 0x0
#define FLASH_SIZE 0x20000
#define RAM_BASE 0x20000000
#define RAM_SIZE 0x5000
#define RAM_END 0x20004A13
#define PAGE_SIZE 0x1000
// Last page is reserved by Application for CCFG.
#define NUM_RESERVED_PAGES 1
#define RESERVED_SIZE (NUM_RESERVED_PAGES * PAGE_SIZE)
/* System memory map */
MEMORY
{
/* EDITOR'S NOTE:
* the FLASH and SRAM lengths can be changed by defining
* ICALL_STACK0_ADDR or ICALL_RAM0_ADDR in
* Properties->ARM Linker->Advanced Options->Command File Preprocessing.
*/
/* Application stored in and executes from internal flash */
/* Flash Size 128 KB */
#ifndef ICALL_STACK0_ADDR
#define ICALL_STACK0_ADDR 0x9000
#endif
FLASH (RX) : origin = ICALL_STACK0_ADDR, length = FLASH_SIZE - RESERVED_SIZE - ICALL_STACK0_ADDR
/* Application uses internal RAM for data */
/* RAM Size 20 KB */
#ifndef ICALL_RAM0_ADDR
#define ICALL_RAM0_ADDR 0x20003800
#endif
SRAM (RWX) : origin = ICALL_RAM0_ADDR, length = (RAM_BASE + RAM_SIZE) - ICALL_RAM0_ADDR
//SRAM (RWX) : origin = ICALL_RAM0_ADDR, length = RAM_END - ICALL_RAM0_ADDR
}
/* Section allocation in memory */
SECTIONS
{
.text : > FLASH
.const : > FLASH
.constdata : > FLASH
.rodata : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.emb_text : > FLASH
EntrySection : > ICALL_STACK0_ADDR
.vtable : > SRAM
.vtable_ram : > SRAM
vtable_ram : > SRAM
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.nonretenvar : > SRAM
}
<IAR files>
- coreEndDevice.cfg
- coreEndDevice.xcl
- cc26xx_app.icf
- cc26xxx_zstack.icf
What can i do about this problem...?