CC2650: CC2650 GPIO Pull Drive pins during low power mode

1&2. All GPIO can be configured as interrupt.
3. Yes.

2) Can we pull/drive any GPIO HIGH during low power mode without any Leakage current into GPIO pins? Please confirm on this.
-----> In which mode we can drive any GPIO high, In STANDBY mode or SHUTDOWN mode?

I am not clear about your question. By default, the I/O driver (output) and input buffer (input) are disabled at power on or reset, and thus the
I/O pin can safely be left unconnected (floating).

My Question is very clear: Is there any Leakage current when GPIO will be HIGH during STANDBY mode and SHUTDOWN mode?

No.

Hi Sumit,

The IOs will retain their state in all power modes. There is no leakage current caused by the device itself, no matter how you configure the pin. External connections can of course cause current leakage though.

Cheers,
Fredrik

Hi Fredrik,

Thanks for confirmation and i agree on point that of course external connections design can cause current leakage.
Is there any document available for this?

Document for what?

Hi Fredrik,

Related to this leakage current, like can we get this info in datasheet and TRM? I am not getting this data in these docs.

Hi Fredrik,

Okay, understood that everything is not documented. I have seen that TRM IO structure and i was clear on that but just for confirmation i was checking because this is battery powered product so taking care more on consumption.
Thanks for support.

Hi Fredrik & YiKai,

Appreciate your response. Let me clarify what Sumit is looking for so that we all can agree on this.

We will have some external pull ups on some of IOs and we want to make sure that they will not cause any leakage current through the chip in low power mode.

As per above explanation, it is clear that IO power will be off inside chip during low power. It means if there is any external pull to an always on power rail, that same level will appear on that IO pin of IC. Now if internal VCC is switched OFF, there is a chance that some leakage current may flow into the IC. This can happen through internal voltage clamping diodes typically used for protection or through a parasitic diode in p-channel MOSFET. So if there is clamping diode from IO pin to internal VCC line, the device will get voltage on that through pull up + clamp/parasitic diode and this will cause leakage. So question here is whether there is a voltage clamp diode or a parasitic diode in PMOS on IO pins in CC2650. I can't find any Ioff feature in datasheet which is typically available in TI's datasheets for standard logic parts. Does it mean that there is no clamp diode inside? This shall clarify everything for everyone.

Thanks

Vinod

Hi Vinod,

Enabling pull-up on an IO will not cause any leakage current in Standby or Shutdown modes.

Regards,
Fredrik