Other Parts Discussed in Thread: Z-STACK,
Hi,
There are two questions need your help:
- We use SPI interface to communicate with CC2530 and the firmware version is Z-Stack Home 1.2.2a. We use USART 1 SPI(P0_2-P0_5) in I/O pin mapping table(figure 1) instead of main pin configuration as figure 2. The SRDY pin is P0_6 and the MRDY pin is hardwired to SS. But CC2530 no any response. Is there any site effect for this hardware design?
Figure 1:
Figure 2:
The file znp_spi.c in Z-Stack Home 1.2.2a has been modified as following:
#define NP_RDYIn_BIT BV(2)
#define NP_RDYIn P0_2
#define NP_RDYOut P0_6
#define NP_RDYOut_BIT BV(6)
void npSpiInit(void)
{
if (ZNP_CFG1_UART == znpCfg1)
{
return;
}
/* Set bit order to MSB */
U1GCR |= BV(5);
/* Set UART1 I/O to alternate 2 location on P1 pins. */
//PERCFG |= 0x02; /* U1CFG */
/* Mode select UART1 SPI Mode as slave. */
U1CSR = NP_CSR_MODE;
/* Select peripheral function on I/O pins. */
P0SEL |= 0x3C; /* SELP0_[5:2] */
/* Give P1 UART1 priority over Timer3. */
//P2SEL &= ~0x20; /* PRI2P1 */
/* Set RDY to inactive high. */
NP_RDYOut = 1;
/* Select general purpose on I/O pins. */
P0SEL &= ~(NP_RDYIn_BIT); /* P0.2 MRDY - GPIO */
P0SEL &= ~(NP_RDYOut_BIT); /* P0.6 SRDY - GPIO */
/* Select GPIO direction */
P0DIR &= ~NP_RDYIn_BIT; /* P0.2 MRDY - IN */
P0DIR |= NP_RDYOut_BIT; /* P0.6 SRDY - OUT */
P0INP &= ~NP_RDYIn_BIT; /* Pullup/down enable of MRDY input. */
P2INP &= ~BV(5); /* Pullup all P0 inputs. */
/* Falling edge on P0 pins triggers interrupt. */
PICTL |= BV(0); /* P0ICON */
/* Trigger an interrupt on MRDY input. */
P0IFG &= ~NP_RDYIn_BIT;
P0IEN |= NP_RDYIn_BIT;
P0IE = 1;
dmaInit();
U1CSR |= CSR_RE;
}
2. We try to modify our SPI hardware pin design to follow CC2530 main pin configuration with default Z-Stack Home 1.2.2a. The initial procedure is follow figure 3 (In CC2530ZNP interface specification.pdf). But CC2530 cannot be initialed successful every time. Sometimes the MOSI signal is correct (use oscilloscope to measure) but the CC2530 no response . Any suggestion to solve this issue?
Figure 3:
Thanks.
