Help with reset reason for MSP430F2xx

Brendan Simon

Other Parts Discussed in Thread: MSP430F2618

I'm trying to determine the reset reason for a MSP430F2618 device, but I'm not getting the results I expect.

I'm reading the IFG1 register at the start of `main()` and logging it to flash. My test involves pressing the reset button and doing a power cycle.

When pressing reset button the value `10` (0x0A) is logged => RSTIF + OSCFault.

When power cycling, the value `11` (0x0B) is logged => RSTIF + OSCFault + WDTIFG.

Is that correct? I wouldn't expect the watchdog flag to be set on a power cycle. Should the OSCFault be set?

How do I determine a power cycle (cold boot) versus and warm boot (e.g. reset pin asserted, watchdog timeout, illegal instruction, etc) ??

Thanks, Brendan.

over 9 years ago

0 Clemens Ladisch over 9 years ago

Guru 316440 points

I would have expected PORIFG to be set.

0 old_cow_yellow over 9 years ago

Guru 58965 points

Not all the bits in IFG1 are the flags for Reset causes. Only PORIFG, RSTIFG, and WDTIFG are.

Not all the flags for Reset causes are in IFG1. For example, KEYV is in FCL3.

0 Brendan Simon over 9 years ago in reply to Clemens Ladisch

Intellectual 570 points

Yes, one would expect PORIFG to be set. I just remembered that the circuit has a battery backup so the power cycle might not actually be a true cold boot. Will have to drag out the schematics and review.

0 Brendan Simon over 9 years ago in reply to old_cow_yellow

Intellectual 570 points

True, IFG1 is not the only register to check, but should be fine just to test the simple cases of asserting the reset pin and cold boot. Once that is working, then I can look at checking all the other causes.

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Help with reset reason for MSP430F2xx