Device stops during production: Vulnerability of 32kHz quartz to capacitive influence?

No response yet.. Apparently there aren't many quartz experts in this forum? Well, maybe there are CC2640 specialists around:

I implemented clock loss detection as described in Reference Manual 6.1.6.1 in void main (void) direct before BIOS_Start():

    // see 6.1.6.1 in reference manual
    // enable clock loss detection
    HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) |= DDI_0_OSC_CTL0_CLK_LOSS_EN;
    // enable reset due to clock loss detection
    HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL) |= AON_SYSCTL_RESETCTL_CLK_LOSS_EN;
    // Warm Reset Converted to System Reset
    HWREG( PRCM_BASE + PRCM_O_WARMRESET) |= PRCM_WARMRESET_WR_TO_PINRESET;

And apparently it works: When I touch the the quartz with moist fingers just shortly, the controller obviously performs a reset. But as soon as I hold my finger for a longer time (>1s), the controller gets in the same state as before: No operation, only a hw reset brings the system in a running state.

So how does the clock loss detection works? Is there a limitation on how long the clock may stop? Is there any possibility to extend this time? Is there anything else I could do to prevent this state?

Regards, any help appreciated

Harald

Hi Harald,

Sorry for the late response.

When CC26xx starts up, the drive strength for the 32kHz will start from max and then slowly decrease this to find the balance between current consumption and clock quality.

Therefore when the device has already started, a finger touch will cause a reset and since your finger is released after the touch, the device will start up again properly.

However, if you have your fingers on top of the device for longer time, then the device might try to start up but could not even drive the 32k xtal with the max drive strength and will just die afterwards.

Following explains how the clock lost detection works:
"
The sclk_lf (32kHz),sclk_mf (internal 500kHz clock derived from sclk_hf) and sclk_hf (48MHz) are used against each other in order to detect a clock loss event by using counters. The counter keeps counting consecutive non-transition events and when its count is equal to the time out value, clock loss even is generated. Whenever there is a transition showing presence of the clock under detection the counter gets cleared instead.
As sclk_lf generates a long period when its source is changed, CLD (clock loss detect)circuit would generate clock loss event by detecting loss of clock. The hardware does not have intelligence to detect clock switch and turn off CLD circuit. This has to be done through SW. An easy way is to disable CLD when sclk_lf is requested to change the source; Detect the completion of source change by observing status bits and then turn-on CLD circuit again.
Timeout details:
• Loss of sclk_lf is flagged when no transitions on sclk_lf are detected for 511 consecutive sclk_mf periods. (approx 1ms)
• Loss of sclk_mf is flagged when no transitions on sclk_lf are detected for 7 consecutive sclk_lf periods. (approx 200us)
"

It's not recommend to touch the xtals when the device is running.

Christin, 

I'm trying to diagnose some device failures where the board is dead and no longer accessible through the JTAG connection.  Is it possible for touching the crystal to result in permanent damage to the crystal or the CC2640?  (If the 32k crystal is present but not operational would that result in the device not being programmable or connectable through the debugger?)

My operators use ESD protection while handling, programming, and soldering the board, but if this failure mode is possible then I would transition to having them use gloves as well during these operations.  

Best regards,

--Allen