Tool/software: TI-RTOS
I posted this last Wednesday (as a reply to an earlier post of mine) but did not receive an answer; I'm posting it fresh here in as a new topic in case the previous one was mis-posted somehow.
I figured out how to configure a GPIO to output an 8-bit value (serially). My C28x main() starts like this:
int main(void) { DGPIO(MAIN_ENTER); // GPIO debug: start of main() InitRAM(); DGPIO(MAIN_COPY); // GPIO debug: before memcpy() memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); DGPIO(MAIN_COPY2); // GPIO debug: after memcpy
I build and flash this code, then run it outside the debugger and watch the GPIO pin with an oscilloscope. On the O-scope I see the MAIN_ENTER and MAIN_COPY codes on the GPIO pin, but I do not see the MAIN_COPY2 code. Here is the text from the linker script file that defines RamfuncsRunStart (et al):
GROUP { ramfuncs { -l F021_API_C28x_FPU32.lib } } LOAD = FLASH PAGE = 0, RUN = L0_S4_RAM PAGE = 1, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart) RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd)
The FLASH page is defined in PAGE 0 as:
FLASH : origin = 0x00130000, length = 0x0000FFF0 // BOOTLOADER FLASH
The L0_S4_RAM block is defined in PAGE 1 as:
L0_S4_RAM : origin = 0x00008000, length = 0x00009000 // on-chip RAM block L0-L3, S0-S4
Before the C28x core is signaled to load its code from flash, the ARM core assigns Shared Memory blocks S0-S4 to the C28x. Based on the map file from the build, the Ramfuncs are ending up in shared memory (S2 and S3):
00135bf2 _RamfuncsLoadStart
0013663c _RamfuncsLoadEnd
00000a4a _RamfuncsLoadSize
0000e5d4 _RamfuncsRunStart
0000f01e _RamfuncsRunEnd
00000a4a _RamfuncsRunSize
Any hints on what I might be doing wrong here?