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RTOS/AM3358: SYSBIOS interrupt handling speed

Guru* 95265 points

Part Number: AM3358
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Champs,

We are debugging a customer issue with on ARM A8 core,

SYSBIOS: 6.52.0.12

Compiler: GNU 6.3.1.

The code likes this:

taskFxn () {

....

Error_init(&eb);
Timer_Params_init(&contTimerParams);

contTimerParams.period = 500; // 

contTimerParams.periodType = Timer_PeriodType_MICROSECS;
contTimerParams.arg = 1;

contTimerParams.startMode = Timer_StartMode_AUTO;

//delayTimerParams.runMode = Timer_RunMode_ONESHOT;
contTimerParams.runMode = Timer_RunMode_CONTINUOUS;

contTimerHandle = Timer_create(2, timeIsr, &contTimerParams, &eb);

if (contTimerHandle == NULL) {
System_abort("Timer create failed");
}

customer application code; 

}

The timeIsr is simply a counter and should not use any cycles. The timer is HWI as seen in ROV view. 

When the contTimerParams.period = 500; , the customer application code following the timer_create can be executed normally. If the contTimerParams.period = 300; the application code can't get chance to run (e.g, set a break point, and can't be hit).

We added a UIA module to track the CPU load. When the timer interrupt interval is 2000 us, the CPU load is already ~70%. When timer interrupt interval is 1500 us, the CPU load is ~100%. Reducing the interrupt interval further, the CPU is totally busy and no CPU load graph can be generated. I believe the UIA module itself takes cycles as well. 

The real usage case for customer is they have interrupt came in every 125 us. 

In SYSBIOS, is there any configuration to let application has chance to run when the there is interrupt happening at fast pace?

Regards, Eric

  • Eric,

    The customer may have hit a hardware limitation. Unfortunately, there is no zero latency interrupt support for the A8.

    Something I may suggest to help reduce the latency is to load the timerISR into cache and lock it. See the SYSBIOS Cache API reference for the A8.

    Another consideration is for the customer to leverage the hardware timer peripheral. Something like using the hardware timer register to maintain the count. (32.768kHz clock with a prescalar of 4 yields ~122 uS). The application can then interrupt at timer overflow (~0) and their application can increment a separate value in RAM.

    Derrick

  • Derrick,

    Thanks for the suggestion! I tried the cache_lock to put ISR into cache, it didn't help. The ISR code is very small. About the timer interrupt, the real customer case is GPIO interrupt from an external device connected. It generated interrupt every 125 us, the A8 needs to handle it. I used the timer interrupt to simulate the GPIO interrupt. Sorry I didn't explain this in the early post. Any another suggestions?

    Regards, Eric

  • Eric,

    Do you know if the customer is attempting to only count GPIO interrupt events (ie Hall effect sensor)?

    The AM335x features an Enhanced Capture (eCAP) Module that is capable is counting such events.

    If the AM335x needs to service each interrupt individually, I worry that they may need another low-power MCU to serve as a co-processor.

    Derrick