EDMA3

Arye Lerner said:

1. The ER, ECR, ESR, IER are all refer to same event map: each bit of those registers represent a fixed hardware event, For example OMAPL137 has bit 31 refers to UART2 Tx, bit 17 for MMCSD tx, etc.

Correct.

Arye Lerner said:

2. DRAE registers are used only if I use shadow regions - I dont need them when I write directly to global registers. Physically, when I write to any register of shadow register I write to Global register, just using different addressing.

Yes, that's more or less correct.  Note, however, if you're using OMAP-L137 that the global region does not have its interrupt connected to any of the processor cores.  If you want to send an interrupt to the ARM you need to use region 0 and if you want to send an interrupt to the DSP you need to use region 1.

Arye Lerner said:

3. when configuring EDMA to be activated by event, like rx from peripheral, I suppose to receive interrupt only on completion of receive, so if  I use UART that has 14 byte FIFO, I will receive EDMA completion interrupt every 14 bytes (if configured this way) - it is impossible to get interrupt only after 100 bytes, unless using chaning or linking.

Right, the completion interrupts will be tied into your ACNT/BCNT values.  Do you have to send 14 bytes to your 14 byte FIFO?  Why not just send 10 bytes at a time?  Normally you wouldn't want to wait for the FIFO to completely empty before refilling.  Is there a reason why it must be sent 14 bytes?  Perhaps this is a bad assumption, but does the FIFO have a programmable threshold in terms of when it requests more data, or does it only have an "empty" signal?