question about dm643x ccdc hd/vd polarity configuration

This is a good question, figure 8 is not as clear as it could be on this so I am not surprised to see the confusion (you are not the first to grapple with the meaning of this figure), the HD and VD signals are actually edge triggered as opposed to level triggered, meaning if you use 'line valid' as HD it reacts to the change from 'line invalid' to 'line valid' (or vice versa with the opposite polarity) in this case followed by counting off the length of the line to capture as opposed to capturing only while 'line valid' is active. The same applies to the frame valid signal with VD, it is the edge that tells the CCDC to prepare to begin clocking in image data, not the fact that it is held in an active state. In the case of figure 8 that you mention it is actually showing a positive polarity, where the start of the frame is shown by the rising edge of HD and VD, at which point the CCDC waits SLVn lines and SPH pixels before actually capturing data, if it was negative polarity the 'valid data area' would be shifted down by SLVn and over by SPH.To put it another way, even though this diagram lines up such that it appears the width of the HD and VD pulses determines the start of the valid data area, there is actually no correlation.

I apologize if this sounds sort of convoluted, this can be hard to explain without a whiteboard :), so to put it more simply, in the case you describe you would want to set the polarity to positive for both HD and VD (i.e. SYN_MODE.HDPOL = SYN_MODE.VDPOL = 0). This implies that the HD and VD signals will go high when you want to capture image data.