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Test Condition: 100Vac with 30% voltage reduction for 500ms (AC source 10% THD) ; Output full load (2400W)
Result: PFC Fets are damage during AC recover
ch1 Bulk Voltage; ch3 inrush FET Ctr; ch5 PFC FET VDS; ch6 AC input Current ch7 LD en (PSon); ch8 Output Load
Question:
1. Why the input current is so noise during AC 100V recycle?
2. Is this issue relate to current loop response/voltage loop response?
Test Condition: 100Vac with 100% voltage reduction for 500ms:
3. Why the PWM change dramatically during AC recover? Is that power limit?
Dear John
Thank you for your reply
The schematic is most likely the same configuration as TI UCC28070 reference. And the controller setting is according to
UCC28070 Excel Applications Design Tool (Rev. A)
We have tried to trimming the voltage loop/current loop/PKlMT. But it still can't solved this issue.
Is it related to Vinac peak and kVFF factors of the controller?
During 70vac, the pin of VINAC (pin5) is around 0.7V.
Hi Keigo,
The Excel document you attached was for a 500W pfc with an 85Vac min input.
Your design is for a 2.4kW application which operates at least to 70Vac.
Also which TI reference design do you refer to ?
With VINAC = 0.7V the multiplier output is zero and the PWM is disabled.
Regards
John
Dear John
Would you provide me your email box address?
I can send you the controller schematic.
That excel is as a design template reference.
Of course, I have changed the parameters
Regards
Keigo
Hi Keigo,
You can send me any relevant information to johngrifftin@ti.com