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Can AM335X GPMC Interface to 512MBytes NAND Flash ?

Other Parts Discussed in Thread: AM3352

Hi,

AM335x TRM, section 7.1.3.3.8.1 describe that "The CS size is programmable from 16MBytes to 256MBytes".

Does that mean interfacing to the MT29F4G08AB is not possible ? This NAND flash has a memory size of 512MBytes (4Gbit) but with only 1 CEn signal ?

Please kindly help to clarify this. Thanks !

- Thomas

  • Hello Thomas,

    NAND devices are not memory mapped so you are not bounded by the GPMC's memory map space in the AM335x.  The GPMC supports up to 16b ECC and 4K page size. so you can use a wide range of NAND devices. 

  • In TRM page 4494, the NAND support max  given is 64Gb

  • Hi,

    Sorry to be resurrecting an old post; however, my questions are related.

    How are NAND flash addresses mapped to GPMC chip selects? For example, AM3352 with a 512MB flash on CS0, 1GB flash on CS1, and 1GB flash on CS2 (all parts have the same organization).

    Would the device tree fragment be correct?

    &gpmc {
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&nand_pins>;
         ranges = <0 0 0x08000000 0x20000000
                   1 0 0x28000000 0x40000000
                   2 0 0x68000000 0x40000000

         >;

     Is the 64Gb limit given in the TRM per chip select?

    Thanks and regards,
    ...doug

  • Doug, the NAND is accessed thru the GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, and GPMC_NAND_DATA registers for each respective chip select.  You would read/write each flash by accessing the appropriate registers for the device's chip select. 

    Note that the 64Gb limit is only for booting, where the ONFI parameters were not available (ie, the ROM must get the NAND parameters from the internal boot table).  

    I'm not sure on the device tree configuration, but i would follow examples from our SDK.

    Regards,

    James