Phy GigaEthernet to replace AR8031 with KSZ9021 (micrel)

Keldy

Ethernet driver is generic and doesn't depend on PHY. If the phy has no errata, then generic phy driver in the linux should work fine.

with regards

Mugunthan V N

Hi Mugunthan,

the ethernet driver is generic in the linux, How about in u-boot ?

Thanks & Regards

Keldy

Keldy

U-Boot CPSW driver is also generic.

with regards

Mugunthan V N

Hi Mugunthan,

After I replace AR8031 phy with micrel KSZ9021RL phy,

in u-boot, when i enter "dhcp",

u-boot#dhcp

link up on port 1, speed 100, full duplex

BOOTP broadcast 1

BOOTP broadcast 2

BOOTP broadcast 3

BOOTP broadcast 4

.....until BOOTP broadcast 10 then repeat again

seen like the ethernet can't work properly and can't get IP address.

Why this will happen?

Do i need to change something in u-boot code, like the phy device id, phyaddr or others thing else?

Thanks & Regards

Keldy

Keldy

U-Boot Supports only EMAC 0 by default. From the logs it shows that Ethernet is connected to EMAC 1.

Did you ported U-Boot to support EMAC 1 from the Porting guide Wiki.

http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#CPSW_EMAC_1_bringup_in_uboot

If you have two eEthernet pinned out, can you try connecting with EMAC0.

with regards

Mugunthan V N

Hi Mugunthan,

The Micrel KSZ9021RL phy is connected to EMAC 0.

i think in u-boot,  the EMAC 0  refer as port 1, EMAC 1 refer as port 2. same as i2c0 refer as i2c-1.

Thanks & Regards

Keldy 

Hi,

I'm using AM335x MPU, that have only one EMAC and two port, port 1 and port 2. The micrel KSZ9021RL phy was connected to the port 1.

Port 1 previously connected to Atheros AR8031 phy which is working properly, when i change to micrel KSZ9021RL phy, the ethernet not working anymore.

Any idea?

Thanks & Regards

Keldy

Keldy

Can you confirm the connection in the Schematics, Because in U-Boot port 1 is referenced to EMAC 1 and not EMAC 0.

Also check if RGMII internal delay is taken care.

with regards

Mugunthan V N

Hi Mugunthan,

here is my connection,

RGMII interface:

For your info, I'm using AM335x EVM board and sdk. 

How to check the internal delay?

Thanks & Regards

Keldy

Look at the gmii_sel register at 0x44e10650. Bits 1:0 select the mode for port1 (rgmii = 10) and bit 4 selects the internal delay. See the Control Module chapter of the TRM.

Steve K.

Hi,

will the internal delay cause my micrel KSZ9021RL phy fail working?

how to verify the RGMII interface is working?

is it the micrel phy not compatible with AM335x ?

Thanks & Regards

Keldy 

Keldy

In U-Boot EMAC 0 is attached to Port 0 in software, but it is showing Port 1is connected.

Can you check the phy address is populated in the devices structure properly. You can look for phy_id in the following location

board/ti/am335x/evm.c:struct cpsw_slave_data cpsw_slaves[] - phy_id

with regards

Mugunthan V N

Hi,

What do you mean check the phy address is populated in the devices structure properly ?

do you mean to use the mdio line to access the register in ethernet phy, and get the phy address?

Thanks & Regards

Keldy 

Hi, after i change my phy addr to 0x00, now link up on port 0.

in u-boot, when i type "dhcp":

U-boot#dhcp

link up on port 0, speed 100, full duplex

BOOTP broadcast 1

BOOTP broadcast 2

......until BOOTP broadcast 10 and repeat again

seem like the micrel phy still not working properly. Any idea?

Thanks & Regards

Keldy

Keldy

Can you disable the RGMII internal delay by enabling the bits in gmii_sel

with regards

Mugunthan V N