We are using the GPMC to interface with a Xilinx FPGA in synchronous 16bit addr/data multiplexed mode. Single writes are performed correctly as confirmed using ChipScope logic analyser within the FPGA. Reads are performed in synchronous burst mode with a burst size of 4. The bus transactions when performing the burst read match exactly the timing diagram in the Technical Reference Manual Figure 7-19 as confirmed using ChipScope logic analyser. We have also monitored correct bus activity at the AD[15..0] pins of the AM335x on the read.
Despite the correct data being presented at the AM335x GPMC bus, the data returned to the system request (ie memory read in software) is always 0. We are reading the FPGA using a modified version of StarterWare bootloader, and simply reading a burst of 4 using the following 'C' :-
unsigned long long int data = 0xffffffffffffffff;
data = *((volatile unsigned long long int*)0x09000000);
where 0x09000000 is the base address for the GPMC CS0.
We can step through the compiled (by CodeComposer) assembler code, and the burst read transaction correctly places non-zero data from the FPGA in the correct place on the bus. If the timings were incorrect I would expect something other than zeros on the bus, unless the GPMC is setup in an illegal state which prevents the read data being latched and returned back to the system.
Does anyone have any ideas why the reads are failing?
GPMC registers are configured as follows :-
Config1: 0xea001200
Config2: 0x00090d02
Config3: 0x00040402
Config4: 0x09050c08
Config5: 0x0109090d
Config6: 0x04040000
Config7: 0x00000f49
