Good morning!!
I have a problem with bandwidth of DDR2 memory, when I use memset the bandwidth is about 60MB/s and when I used a for loop to clear an array the bandwidth is about 20MB/s.
In both cases this bandwidth is extremely low, i try to call "CacheEnable(CACHE_ALL)" but absolutely no effect.
the sequence to initialize is:
MMUConfigAndEnable();
CacheEnable(CACHE_ALL);
The dma transfers and raster work at full sped of DDR2 ram memory but bandwidth between MCU and this memory is extremely low.
I try all optimizations but no increase of bandwidth.
If anyone know how to fix this issue please respond to this thread.
Thank you very much.
