I want to set the USBSS.SYSCONFIG soft_reset bit and then poll that same register waiting for the reset to complete. However, this appears to be causing a crash.
It looks like the problem occurs when i try to read back the USBSS.SYSCONFIG register while the soft_reset is still active.
- AM335x
- USBSS.REVREG = 0x4ea2080d
- USBSS.SYSCONFIG register is address 0x4740_0010
- soft_reset is bit[0] of this USBSS.SYSCONFIG register
TRM (spruh73f.pdf section 16.5.1.2 ) states USBSS.SYSCONFIG[0] is Soft_reset
Software reset of USBSS, USB0, and USB1 modules
Write 0 = no action
Write 1 = Initiate software reset
Read 0 = Reset done, no action
Read 1 = Reset ongoing USBSS SIGCONFIG Register
I do something like
- reg = HWREG(0x47400010); //returns default/reset value of 0x28
- reg |= 1; //OR in the soft_reset bit
- HWREG(0x47400010) = reg;
- reg = HWREG(0x47400010); //this will cause a crash
however, if i add some delay between the write to USBSS.SYSCONFIG and the readback, it passes
- reg = HWREG(0x47400010); //returns default/reset value of 0x28
- reg |= 1; //OR in the soft_reset bit
- HWREG(0x47400010) = reg;
- delay();
- reg = HWREG(0x47400010); //this will NOT crash, instead it returns 0x28 (reset not active)
I suspect the crash is caused by trying to read the USBSS while the soft_reset is still actively resetting the block.
However, the TRM implies i can poll this bit to determine when the reset is complete.
