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AM335x with 8-bit NAND

Other Parts Discussed in Thread: AM3354, SYSCONFIG

Hello,

I'm using the AM3354 device with a 8-bit NAND flash, what are the changes I need to make to the U-boot/SPL code. The only define I came across is GPMC_NAND_ECC_LP_x16_LAYOUT, which is defined in the am335x_evm.h file. I have changed it to be x8 instead.

Are there any other changes that I need to make??

Thank you

Regards

Santhosh

  • Hello Everyone,

    Some additional information, I'm using SDK version 5.05.00.00. When I compile the code it gives me an error at line 54 in ti81xx_nand.c. See below

    ti81xx_nand.c:54:44: error: 'GPMC_NAND_HW_ECC_LAYOUT_KERNEL' undeclared here (not in a function)

    If you look at this file, there is a structure defined which is initialized to GPMC_NAND_ECC_LAYOUT_KERNEL. This macro is defined in nand.h under arch-ti81xx folder.

    However, this definition is only defined for the x16 devices, it's enveloped in #ifdef GPMC_NAND_ECC_LP_x16_LAYOUT. Since my board has a x8 NAND device this definition is not present.

    So my question is, can I remove the #ifdef so that it includes it for both x8 and x16 devices or is there a specific definition for the x8 device.

    Thank you for your replies.

    Regards

    Santhosh

  • Hello Guys,

    Any update on this one??

    Regards

    Santhosh

  • I have another questions to add, in the function gpmc_init defined in arch/arm/cpu/armv7/ti81xx/mem.c, I'm having difficulty understanding the values written to the IRQSTATUS and IRQENABLE registers. From the TRM it seems that Wait0 interrupt status is reset and then Wait1 interrupt is being set.

    /* global settings */
        writel(0x00000008, &gpmc_cfg->sysconfig);
        writel(0x00000100, &gpmc_cfg->irqstatus);
        writel(0x00000200, &gpmc_cfg->irqenable);
        writel(0x00000012, &gpmc_cfg->config);

    Can someone confirm this, I'm only using WAIT0, so should I enable Wait0 instead of Wait1.

    Thank you

    Regards

    Santhosh

  • I see no ones replying... so I'm just gonna update this thread for anyone else who is using 8-bit NAND.

    I have the NAND successfully working..with the modifications indicated above. I also changed the irqenable to use WAIT0 instead of WAIT1.

    I have only tested U-boot and SPL so far, and I have not tested the Linux kernel yet...will post the results when I do.

  • Thanks for the information.

     I'm going to use a 8bit flash in my design and was just worried about the implications, as the eval. board uses a 16-bit flash.

    I guess Linux i booting without problems, it's just the boot that needs to be modified...

  • Please do let me know how the Linux boot works. I think I got it to boot successfully but I don't remember now, I'm since then working on a different project and will  come back to this in March.

    Good luck.

    Regards

    Santhosh