Ethernet problem in U-Boot - can't ping

I have a custom board that uses the AM3352 and has two Ethernet ports, one with sn SMSC LAN8720Ai phy and the other with a TI TLK106 phy.  I believe I've modified the pinmux settings for RMII correctly.

After setting an IP address in U-Boot and performing a ping to a host I know is up, I'm not getting a response, but do get output indicating something is occurring:

U-Boot# setenv ipaddr 192.168.98.200
U-Boot# ping 192.168.98.14
entered cpsw_control line 649
link up on port 0, speed 100, full duplex
Using cpsw device
entered cpsw_control line 649
ping failed; host 192.168.98.14 is not alive

Can anyone suggest how to debug this?  Hardware is brand new and untested apart from being able to boot u-Boot and the kernel.  Wireshark indicates no outbound traffic from the board.

  • Hello Sean,

    How are you sourcing the 50MHz RMII clock?

    Did you perform a timing analysis of the RMII interfaces prior to board fab?

  • In reply to -DK-:

    Ah yes been told by the hardware guys that the board is not currently wired up for the 50MHz clock.

    There is a 25MHz crystal that goes to the LAN8720A(i) phy chip.  There is an MDIO_CLK signal that comes from the CPU and goes to the phy chip, I assume that's the pin we want the 50Mhz signal on?  If yes, what type of config. beyond what's being done on the BeagleBone or SK EVM is needed to get the 50Mhz signal?

  • In reply to Sean Machin:

    The MDIO clock (MDC) is sourced by the AM335x; no external clock source is needed for this interface.  MDIO is a bussed interface so both PHYs share the same clock and data signals. 

    The LAN8720a can derive a 50Mhz clock from an attached 25MHz crystal, which can then be used to source the AM335x's 50MHz RMIIx_REFLCK input via its REFCLKO pin. The TLK106 does not have this capability and as such a 50MHz reference clock must be supplied. It may be possible to also use the LAN8720a 50MHz output (REFCLKO) as an input to both the TLK106 and the associated AM335x MAC reference clock input, but SMSC does not publish the jitter specifications for this output clock so you may run into jitter and/or timing issues due to the associated increase in trace length and device loads. Extra care would need to be taken to ensure that trace lengths are reasonable and that a timing analysis reveals no problem with this solution.

    Given the two PHYs that you have chosen to use on your board, the easiest solution would be to use a single discrete LVCMOS 50MHz, 50ppm, low jitter oscillator to source the reference clocks to both AM335x RMII_REFCLK pins and both PHYs. 


  • In reply to -DK-:

    I checked the 50MHz and 25MHz clock signals and they looked OK.  My schematic for eth0 at http://resplendid.com/eth0.png.

    What needs to be configured in the software to get RMII to work?  I believe I have my pinmux settings correct (see below), perhaps I am missing something?

    /* Module pin mux for rmii1 */
    static struct pinmux_config rmii1_pin_mux[] = {
            {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
            {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
            {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
            {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
            {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
            {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
            {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
            {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
            {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
            {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
            {NULL, 0},
    };

  • In reply to Sean Machin:

    From a quick glance, the pin mux looks correct. Look around in u-boot for the gmii_sel register. This selects whether you are using mii/rmii/rgmii. Only beaglebone < A3 use RMII; all others use MII.

    Steve K.

  • In reply to Sean Machin:

    Have you selected RMII mode by setting the respective GMIIx_SEL bits in the GMII_SEL register to "01"? 

    Have you selected RMII reference clock input mode by setting the respective MIIx_IO_CLK_EN bit in the GMII_SEL register to "1"?

    Regards,
    Paul

  • In reply to peaves:

    I have the gmii_sel register set to 0xc5, is that right?

  • In reply to Sean Machin:

    You have bits 4 and 5 set to "0" which the TRM shows to be a reserved value for these bits, but this should not cause an issue since these only affect RGMII mode.  However, I would recommend you change the value to 0xF5 to be consistent with the TRM.

    Regards,
    Paul

  • In reply to peaves:

    Yes tried F5, no difference.  Are there any type of registers that can be read to further probe what's going on?

  • In reply to Sean Machin:

    Do you have access to a logic analyzer that can be connected to the RMII signals?

    If so, it may be helpful if you can monitor the RMII signals with a logic analyzer while sending and receiving known data packets to confirm the data transferred between the PHY and AM335x matches the expected data.

    Regards,
    Paul