• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 101 subscribers
  • Views 13488 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[AM335x] Board Porting - BeagleBone MII to 2xRMII

Michael Questo
Expert 6000 points
Other Parts Discussed in Thread: TLK106

Hello again AM335x Champs,

Were having trouble bringing up my dual RMII ports. We have designed the board using the Beaglebone as a reference and are running Linux PSP 5.06.

We are currently using two PHYs a LAN8710AI (Note: this is not the LAN8720 found on the Beaglebone) and a TLK106.

We have been testing the device using WireShark  running on a local PC and TCP Dump running on the device.
- Using WireShark - We are able to see DHCP requests but not any positive DHCP responses to those requests  
- Using TCP Dump - We are able to see Tx packets only and no received

We beleive there are three difference avenues for this to fail: Hardware, PinMux, and Linux Confuration.  We woud like you guidance in helping us identify which of these areas is having an issue.  I have already submitted the schematics for review, so let's focus on the ladder two.

PinMux:
1. Did we configure the PinMux correctly for dual RMII + MDIO communication? (Board files and PinMux below)
Linux/AM335x Configuration:
2. Are there additional kernel/AM335x settings required to change MII to RMII beyond the pinmux?
- How does linux kernel know to configure the MAC to use RMII instead of MII, is this done automatically in the board file by adding the correct mux settings?
3. The PSP 5.06 that was taken from BeagleBone uses LAN8710 PHY, however, we are using a LAN8720 is there any difference in the MDIO driver?
4. Is there Kernel Menu Config setting for Ti's TLK106?
- There doesn't seem to be an entry in the 5.06 PSP kernel config menu
 
  • 0
    TI__Mastermind 27890 points

    Michael,

    This seems very much like the same issue: http://e2e.ti.com/support/arm/sitara_arm/f/791/p/260419/913521.aspx#913521

    Are they related?

  • 0 in reply to -DK-
    Intellectual 995 points

    This is Sean here, I am the customer and Michael is our FAE.  Yes it's the same issue.

    I would also add that we see differences board to board - my original board is able to transmit but not receive, but on other boards we can't transmit at all, and the Ethernet interface comes up as eth2,3 or eth6,7 instead of the expected eth0,1 in Linux.

    We have verified that there is serial communications between the CPU and the PHY (mdio_clk and mdio_data).

    I also notice in the board file that for old BeagleBons they make this call:

            phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
                                            beaglebone_phy_fixup);

    before calling am33xx_cpsw_init.  What does the above call do exactly and do we need it for our RMII 8720 & TLK106 configuration?

  • 0 in reply to Sean Machin
    TI__Expert 6000 points
    Quick debug update:
    We are able to see I2C like activity on the MDIO CLK and DATA lines with a scope so that would provide reason to beleive that the pinmux was set correctly.
     
    DK,
    Yes these posts are related.
  • 0 in reply to Michael Questo
    Intellectual 995 points

    I did some research over the weekend and now have the first ethernet port eth0 working in RMII mode with the SMSC 8720A PHY.  This setup only works if I define a static network address (no DHCP), then issue an /etc/init.d/networking restart after the system has booted.

    So some follow up questions:

    1. Why must the network be restarted to get it to work?
    2. Why is it not working for DHCP?
    3. How do you enable support for TI's TLK106 Phy in the PSP package?
    4. Download speed is only about 12.5KB/sec to download an iso from http://cdimage.debian.org/debian-cd/7.0.0/i386/iso-cd/debian-7.0.0-i386-CD-1.iso.  On my Desktop PC I am getting 316KB/sec
    5. Output from an ifconfig eth0 shows quite a number of dropped frames, does this indicate a problem?

    eth0      Link encap:Ethernet  HWaddr bc:6a:29:57:3e:dc
              inet addr:192.168.98.200  Bcast:192.168.98.255  Mask:255.255.255.0
              inet6 addr: fe80::be6a:29ff:fe57:3edc/64 Scope:Link
              UP BROADCAST RUNNING ALLMULTI MULTICAST  MTU:1500  Metric:1
              RX packets:3221 errors:0 dropped:272 overruns:0 frame:0
              TX packets:254 errors:0 dropped:0 overruns:0 carrier:0
              collisions:0 txqueuelen:1000
              RX bytes:465093 (454.1 KiB)  TX bytes:20375 (19.8 KiB)

  • 0 in reply to Sean Machin
    TI__Expert 6000 points

    To address Item #2

    "Are there additional kernel/AM335x settings required to change MII to RMII beyond the pinmux?"

    Section 9.3.31 gmii_sel Register  in the TRM describes the AM335x registers that must be set to configure the MII correctly.

    AM335x Technical Reference Manual:

  • 0 in reply to Michael Questo
    Intellectual 995 points

    Hi Mike,

    Yes I located the section in the board file where we have to set RMII, MII or RGMII mode and believe it's set correctly (had TI verify the register value).

    Still got some outstanding problems on the Ethernet, see the thread:

    http://e2e.ti.com/support/arm/sitara_arm/f/791/p/260419/921260.aspx#921260

  • 0 in reply to Sean Machin
    TI__Expert 6000 points

    We've identified the issue.

    It turned out that the REFCLK was sourcing a 50 MHz clock that was colliding with the 50 Mhz Clock sourced by the LAN8720.

    The AM335x is not capable of sourcing the REFCLK which is stated in the Errata below and requires that it is sourced by the PHY for RMII operation

    Since our current prototypes are using PG 1.0 Silicon the RMII_IO_CLK_EN pin will be set to 0 by default.  This will result in both REFCLKs sourcing the 50 Mhz Clock waveform. 

     In order to resolved this we had to set the rmii1_io_clk_en and  rmii2_io_clk_en bits to 1 in both the Uboot and the Kernel.

    The RMII Control registers can are controlled by the following register which is explained in the TRM (http://www.ti.com/lit/ug/spruh73h/spruh73h.pdf)
    Section 9.3.31 gmii_sel Register
    1.2.10 Changed Default Value of RMII Clock Source
    Section 9.3.31, gmii_sel Register and Errata Advisory 1.0.18.
    PG1.0: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 0.
    PG2.x: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 1.

     

    Advisory 1.0.16 RMII: 50-MHz RMII Reference Clock Output Does Not Satisfy Clock Input Requirements of RMII Ethernet PHYs

     

    REFCLK Sourced by the AM335x (Isolated):

    REFCLK Sourced by the LAN8720 (Isolated):

    REFCLK Collision:

  • 0 in reply to -DK-
    Prodigy 10 points

    Was the interface to the TLK106 completed under the Beaglebone setup (EZLinux)?