On some of our AM3354ZCZD72 boards the frequency of the peripheral PLL changes by +25% without any new values being written to the registers.
1. We detected the baudrates of all serial ports increasing by 25%, also the clock of the MMCx (µSD and SD cards) increased from 24MHz to 30MHz and USB not working.
2. Clocks for LCD, ASPx, CAN, PWM and even the 26MHz oscilator are correct and stable.
3. Reading the register values of the per PLL in good and bad condition showed no difference, same divider and lock bit set. (No firmware write these registers after boot)
CM_DIV_M2_DPLL_PER (0x90a004ac) : 0x00000285
CM_CLKMODE_DPLL_PERR (0x90a0048c) : 0x00000007
CM_CLKSEL_DPLL_PER (0x90a0049c) : 0x0403c019
CM_IDLEST_DPLL_PER (0x90a00470) : 0x00000001
4. If the regsiter CM_CLKSEL_DPLL_PER is again initialised the correct way (bypass, write, lock....) with the same value the baudrates / clocks become again correct in frequency.
OUTREG32(PA_CM_CLKMODE_DPLL_PER, PLL_BYPASS_MODE);
while(INREG32(PA_CM_IDLEST_DPLL_PER) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
OUTREG32(PA_CM_CLKSEL_DPLL_PER, clksel);
div_m2 = div_m2 & ~0x7f;
div_m2 = div_m2 | PERPLL_M2;
OUTREG32(PA_CM_DIV_M2_DPLL_PER, div_m2);
clkmode = clkmode | 0x7;
OUTREG32(PA_CM_CLKMODE_DPLL_PER, clkmode);
while(INREG32(PA_CM_IDLEST_DPLL_PER) != 0x1);
I can only concluded this would happen if the peripheral PLL is not running correctly internally in hardware ?
Who can give me some more info on the per-PLL internal working please (power pin, lock, ....)
