AM335X outer cache behaviour

Hello,


I am working on the MINIX port to the AM3559 Beagle Bone black and have been fighting the following
problem.

I have configured the MMU system to work without TEX remap (e.g SCTRL_TRE=0) and I am marking main memory
as cacheable. Idealy I would like to mark the memory write back but currently I am simply marking memory as
write trough cacheable. I do this by setting TEX2 TEX1 and  C bits to 1 (inner and outer write-through, no write-allocate).
To keep things simple I also disabled the I_CACHE.

I am running into all kinds of strange problems when changing the page tables or the page table translation base register ttbr0. These problems result data corruption or crashes.
It looks like the MMU fetches do not see my changes although I properly use memory barriers as documented in the TRM
e.g.  change something to the page table,do a dsb, invalidate the TLB (I do this using a TLBIALL),do a second DSB  and do an ISB

I can fix the problem by not enabling the outer cacheability of the mapped memory e.g. only set TEX2 and the C bit and I am clueless why
disabling the outer cache helps resolving my issues.

I have the following question:
How can I ensure the MMU fetches the correct data without disabling the outer cache?
Should the TTBR0 cacheability bits match the way I map normal memory?
I have not use the shareability bits in neither the page table nor the ttbr is this necessary?

Thanks