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kernel configure 2 Ethernet ports in am335x

daniel formolo
Intellectual 805 points
Other Parts Discussed in Thread: TS5A3157

Hi guys,

We have a hardware with 2 ethernet ports: 

PORT 0: RGMII, phy adress 0

PORT 1: RMII, phy adress 3

I changed kernel to accept them, but only PORT 0 works. Bellow the modifications:

-----------> in arch/arm/mach-omap2/board-am335xevm.c

/* Module pin mux for rmii1 */
static struct pinmux_config rmii1_pin_mux[] = {
//df db
{"gpmc_csn3.rmii2_crs_dv", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_wpn.rmii2_rxerr", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a0.rmii2_txen", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
{"gpmc_a4.rmii2_txd1", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
{"gpmc_a5.rmii2_txd0", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
{"gpmc_a10.rmii2_rxd1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
{"gpmc_a11.rmii2_rxd0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_col.rmii2_refclk", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0},
};

static void rmii1_init(int evm_id, int profile)
{
    setup_pin_mux(rmii1_pin_mux);
    return;
}

/* Industrial Auto Motor Control EVM */
static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
    {am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {clkout2_enable, DEV_ON_BASEBOARD, PROFILE_ALL},
    {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {lcdc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {gpio_ddr_vtt_enb_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {rmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {spi1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {matrix_keypad_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    // {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
    // {haptics_init, DEV_ON_BASEBOARD, (PROFILE_4)},
    {sgx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {NULL, 0, 0},
};

 

 


static void setup_ind_auto_motor_ctrl_evm(void)
{
    ...
    am33xx_cpsw_init(AM33XX_CPSW_MODE_RMII, "0:00", "0:03");
}



-----------> in arch/arm/mach-omap2/devices.c

static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
{
.slave_reg_ofs = 0x200,
.sliver_reg_ofs = 0xd80,
.phy_id = "0:00",
.dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_0,
},
{
.slave_reg_ofs = 0x300,
.sliver_reg_ofs = 0xdc0,
.phy_id = "0:03", // <------------------------- CHANGED HERE
.dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_1,
},
};



-----------> in arch/arm/mach-omap2/mux33xx.c

...  ORIGINAL:
// _AM33XX_MUXENTRY(GPMC_CSN3, 0, "gpmc_csn3", NULL, NULL, "mmc2_cmd", NULL, NULL, NULL, "gpio2_0"),

...  CHANGED HERE:
_AM33XX_MUXENTRY(GPMC_CSN3, 0, "gpmc_csn3", "rmii2_crs_dv", NULL, "mmc2_cmd", NULL, NULL, NULL, "gpio2_0"),

I can configure an IP and Mask, Linux identify signal UP and signal DOWN, but ping or any other comunication command doesn't work for PORT 1.

Am I missing something or coded in wrong way PORT 1?

Note that AM33XX_CPSW_MODE_RMII configures  RMII for both ports. How can I configure CPSW to RMII -> port 1 and RGMII port 0??

 

thanks for your help in advanced.

 

daniel.

  • 0
    TI__Guru**** 393215 points
    Hi Daniel,
     
    Are the two PHYs on different subnets?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 805 points

    Hi Biser, yes it is. Bellow is the ethX configuration. Note that eth0 (phy address 0, RGMII) allways work well. The problem is eth1 (phy adress 3, GMII).

    Is it ok change arch/arm/mach-omap2/mux33xx.c? I needed to add a new pin to GPMC_CSN3 configuration to be compatible with the hardware:

    _AM33XX_MUXENTRY(GPMC_CSN3, 0, "gpmc_csn3", "rmii2_crs_dv", NULL, "mmc2_cmd", NULL, NULL, NULL, "gpio2_0"),

     

    ----------------------------------------------------------------------

    root@am335x-evm:~# ifconfig
    eth0 Link encap:Ethernet HWaddr C4:ED:BA:7D:7A:04
    inet addr:192.168.1.190 Bcast:192.168.1.255 Mask:255.255.255.128
    UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
    RX packets:207 errors:0 dropped:37 overruns:0 frame:0
    TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
    collisions:0 txqueuelen:1000
    RX bytes:40388 (39.4 KiB) TX bytes:0 (0.0 B)

    eth1 Link encap:Ethernet HWaddr C4:ED:BA:7D:7A:05
    inet addr:192.168.1.90 Bcast:192.168.1.127 Mask:255.255.255.128
    UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
    RX packets:0 errors:0 dropped:0 overruns:0 frame:0
    TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
    collisions:0 txqueuelen:1000
    RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

    lo Link encap:Local Loopback
    inet addr:127.0.0.1 Mask:255.0.0.0
    UP LOOPBACK RUNNING MTU:16436 Metric:1
    RX packets:39 errors:0 dropped:0 overruns:0 frame:0
    TX packets:39 errors:0 dropped:0 overruns:0 carrier:0
    collisions:0 txqueuelen:0
    RX bytes:4368 (4.2 KiB) TX bytes:4368 (4.2 KiB)

  • 0 in reply to daniel formolo
    TI__Guru**** 393215 points
    Hi Daniel,
     
    Here is what the factory team suggested on your issue:
     
    "Can he talk to the RMII PHY via MDIO? If so, please ask him to dump the PHY registers and compare the settings to the MAC side to make sure both sides of the interface are aligned."
  • 0 in reply to Biser Gatchev-XID
    Intellectual 805 points

    Biser, we have 2 independent PHYs, all packages transmitted/received  are changed by eth0 (192.168.1.188). Even the packages addressed to eth1 (192.168.1.88). Could this confusion happens because the "Ethernet Switch Driver" who manage the PHYs.  Kernel calls the function am33xx_cpsw_init?

    the data of eth1 are arrive to am335x in the correct pins, as configured in pinmux.

    thanks for your attention.

  • 0 in reply to daniel formolo
    Intellectual 805 points

    We follow the document:

    http://processors.wiki.ti.com/index.php/AM335x_CPSW_%28Ethernet%29_Driver%27s_Guide

    and checked: Dual Standalone EMAC mode

    Configuration is ok. But seems that the look up table of CPSW isn't configured to send packets for eth1, all packets independently of mac adress are send to eth0

     

     

  • 0 in reply to daniel formolo
    TI__Guru**** 393215 points
    Daniel,
     
    What is your network topology? How are the two PHYs connected to the network?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 805 points

    Hi Biser.

    I tried some topologies:

    TOPOLOGY 1

    - eth0: 192.168.1.190 netmask 255.255.255.128

    - eth1: 192.168.1.90 netmask 255.255.255.128

    - both linked to local network and tried to ping a PC adressed to 192.168.1.164 netmask 255.255.255.0

    - the PC ping only eth0. 

    - eth0 ping PC.

    * eth0 also responds to IP 192.168.1.90. The ethernet packet arrives to PC with IP=192.168.1.90 and MAC address of eth0.

    * if eth0 is disconnected nothing works.

    TOPOLOGY 2

    - eth1: 192.168.1.90 netmask 255.255.255.0

    - eth1 conected point-to-point with PC 192.168.1.164 netmask 255.255.255.0

    - nothing works.

    TOPOLOGY 3

    - eth1: 192.168.1.90 netmask 255.255.255.0

    - eth1 conected point-to-point with a test-set equipment that generate ethernet traffic.

    - eth1 not responds.

    TOPOLOGY 4

    - eth0: 192.168.1.90 netmask 255.255.255.0

    - eth0 conected point-to-point with a test-set equipment that generate ethernet traffic.

    - eth0 responds very well.

    TOPOLOGY 5

    - ping localhost to both eth0 and eth1: all responds ok. But I suspect that eth1 responds over eth0.

    TOPOLOGY 6

    - enable in kernel only the eth1 phy address, nothings works.

    - enable in kernel only the eth0 phy address, works well.

    other less important alternatives were try. Seems that the internal switch redirect all packets to eth0. 

    important: we measured the signals of eth1 and they arrive to am335x in the correct pins. The data are arriving to am335x that ignores them.

    - We intend that the phys work independently.

    - Any VLAN or package forwarding was created. 

  • 0 in reply to daniel formolo
    TI__Guru**** 393215 points
    Daniel,
     
    I asked the factory team to take a look at your last post. Here is their comments:
     
    They cannot have both interfaces connected to the same subnet. As they have noticed all traffic is seems to happen on one port, the first one. The kernel filters which port to send data on by the subnet and the first interface it finds with a matching subnet. Ask them to get a second router and setup a second subnet.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 805 points

    ok Biser, bellow is the log of the 2 VLANs. In fact, the VLANs are created, but the error continues. That is very odd. Now I am working to print the switch registers and informations about the real set up configuration.

    We also changed uboot -> board.c in:

    /* MII mode defines */
    #define MII_MODE_ENABLE 0x0
    #define RGMII_MODE_ENABLE 0XF6    <--------- this register to  work with RGMII and RMII ports.

    is there another places in uboot that we need pay attention? 

    [ 16.402496] ------------------------> cpsw_add_dual_emac_mode_default_ale_entries
    [ 16.411926]
    [ 16.411926] ------------------------>slave->port_vlan 2
    [ 16.418731] ------------------------>priv->ale c77a7ec0
    [ 16.424835] ------------------------>priv->host_port 0
    [ 16.430297] ------------------------>priv->mac_addr c4 ed ba 7d 7a 4
    [ 16.442413] ------------------------>slave_port 1
    [ 16.451263] net eth0: CPSW phy found : id is : 0x4dd074

    _____ _____ _ _
    | _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
    | | _| .'| . | . | | __| _| . | | | -_| _| _|
    |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
    |___| |___|

    Arago Project http://arago-project.org am335x-evm ttyO0

    Arago 2013.05 am335x-evm ttyO0

    am335x-evm login: root
    root@am335x-evm:~# ifconfig eth1 192.168.1.90 netmask 255.255.255.128 up
    [ 55.256439]
    [ 55.256469] ------------------------> cpsw_add_dual_emac_mode_default_ale_entries
    [ 55.265930]
    [ 55.265930] ------------------------>slave->port_vlan 3
    [ 55.272766] ------------------------>priv->ale c77a7ec0
    [ 55.278869] ------------------------>priv->host_port 0
    [ 55.284332] ------------------------>priv->mac_addr c4 ed ba 7d 7a 5
    [ 55.296447] ------------------------>slave_port 2
    [ 55.304382] net eth1: CPSW phy found : id is : 0x221560

     

  • 0 in reply to daniel formolo
    Intellectual 805 points

    Biser. we found a pin conflit in ind_auto_mtrl_evm_dev_cfg struct. Now we can transmit packages, but don't receive.

    - PHY send the signals to am335x

    - PinMux Utility connected GPMC_CSN3 to rmii2_crs_dv MUX1

    - we found in kernel mux33xx.c:

    _AM33XX_MUXENTRY(GPMC_CSN3, 0,
     "gpmc_csn3", NULL, NULL, "mmc2_cmd",
     NULL, NULL, NULL, "gpio2_0"),

      it does not have rmii2_crs_dv, so we included in _AM33XX_MUXENTRY(GPMC_CSN3, but seems does not effect.

    - The _AM33XX_MUXENTRY of mux33xx.c is only for MUX0.

    - All other pins are configured for MUX0, and that is ok, except GPMC_CSN3 to rmii2_crs_dv MUX1

    - how fix GPMC_CSN3 to rmii2_crs_dv MUX1?

    - Bellow the configuration in board-am335x.c

    /* Industrial Auto Motor Control EVM */
    static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
    {am335x_rtc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {clkout2_enable, DEV_ON_BASEBOARD, PROFILE_ALL},
    {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {lcdc_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {gpio_ddr_vtt_enb_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {rmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {spi1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {sgx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
    {NULL, 0, 0},
    };

    /* Module pin mux for rmii */
    static struct pinmux_config rmii_pin_mux[] = {
    //df db
    // {"gpmc_csn3.rmii2_crs_dv", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
    {"gpmc_wpn.rmii2_rxerr", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
    {"gpmc_a0.rmii2_txen", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
    {"gpmc_a4.rmii2_txd1", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
    {"gpmc_a5.rmii2_txd0", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
    {"gpmc_a10.rmii2_rxd1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
    {"gpmc_a11.rmii2_rxd0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLDOWN},
    {"mii1_col.rmii2_refclk", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
    {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
    {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},

    {NULL, 0},

    };

  • 0 in reply to daniel formolo
    TI__Mastermind 40360 points

    I could not follow your updated mux entry, does it look like this?

    _AM33XX_MUXENTRY(GPMC_CSN3, 0,
                    "gpmc_csn3", NULL, "rmii2_crs_dv, "mmc2_cmd",
                    NULL, NULL, NULL, "gpio2_0"),

    is the line rmii2_crs_dv commented out in the pin mux structure?

  • 0 in reply to Schuyler Patton
    Intellectual 805 points

    Yes Patton, we added rmii2_crs_dv to _AM33XX_MUXENTRY(GPMC_CSN3.

    in windows pinmux software that is a valid option. In kernel we changed _AM33XX_MUXENTRY(GPMC_CSN3 to accept it. But that change doesn't work.

    -> linux evm version 06.00.00.00

    - What is wrong: pinmux software or mux33xx.c? 

    - It is possible change am33xx_muxmodes[] to accept other pin connections?

    best regards

     

     

  • 0 in reply to daniel formolo
    TI__Mastermind 40360 points

    You should be able to change the am33xx_modes entries.

    Could you post the complete entry that you have for  _AM33XX_MUXENTRY(GPMC_CSN3 ?

  • 0 in reply to Schuyler Patton
    Intellectual 805 points

    Hi, in bold is the modification. Could you see the first message of this track. There, it s explained in details.

    the new register:
    _AM33XX_MUXENTRY(GPMC_CSN3, 0,
    "gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd",
    NULL, NULL, NULL, "gpio2_0"),

    the original register:
    // _AM33XX_MUXENTRY(GPMC_CSN3, 0,
    // "gpmc_csn3", NULL, NULL, "mmc2_cmd",
    // NULL, NULL, NULL, "gpio2_0"),

    but, that doesn't change the board behaivor. Is there a way to verify if rmii2_crs_dv is really linked to GPMC_CSN3?

  • 0 in reply to daniel formolo
    Intellectual 805 points

    Dears, in order to resolve GPMC_WAIT0 conflit  We found some suggested solutions:

    HARDWARE SOLUTION 1:

    sprz360f.pdf : 

    SitaraTM AM335x ARM® CortexTM-A8
    Microprocessors (MPUs)
    Silicon Revisions 2.1, 2.0, 1.0
    Silicon Errata

    ITEM: 3.1.6

    Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue
    The AM335x device multiplexes the GPMC_WAIT0 and GMII2_CRS signals on the same terminal. This
    causes a problem when the system must support NAND boot while an MII Ethernet PHY is connected to
    port 2 of the Ethernet media access controller and switch (CPSW). The GPMC_WAIT0 signal is required
    for NAND boot. The GMII2_CRS signal is required by the MII Ethernet PHY and the only pin multiplexing
    option for these signals is GPMC_WAIT0.
    In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND
    READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS
    output must source the GPMC_WAIT0 terminal when the application software is using port 2 of the
    CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the system to
    select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to have an
    internal or external resistor that selects the NAND READY or BUSY output as soon as power is applied
    and remains in that state until the application software initializes the CPSW.
    The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.
    This device inserts minimum propagation delay to the signal path since it is an analog switch. The
    propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing
    violations for the respective interface.
    The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and
    2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share
    common signals.

    * similar solution is described in post: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/154191.aspx

    PINMUX SOLUTION 1:

    In manual: spruh73j.pdf

    AM335x ARM® CortexTM-A8 Microprocessors
    (MPUs)
    Technical Reference Manual

    ITEM: 1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing

    PINMUX SOLUTION 2:

    At same time, the bellow discussed along thas posts, is another alternative.

    the new register:
    _AM33XX_MUXENTRY(GPMC_CSN3, 0,
    "gpmc_csn3", NULL, "rmii2_crs_dv", "mmc2_cmd",
    NULL, NULL, NULL, "gpio2_0"),

    the original register:

    // _AM33XX_MUXENTRY(GPMC_CSN3, 0,
    // "gpmc_csn3", NULL, NULL, "mmc2_cmd",
    // NULL, NULL, NULL, "gpio2_0"),

    NOTE: for us, SOFTWARE SOLUTION 1 and 2 does not work.

    So, I ask you: Is there a solution via pinmux configuration (SOFTWARE SOLUTION 1 or 2) ?  or the only solution is HARDWARE SOLUTION 1?

  • 0 in reply to daniel formolo
    TI__Guru 63155 points

    Your original post mentions Port 0 and Port 1.  However, the external CPSW ports on AM335x are numbered 1 and 2 with port 0 being the internal port of CPSW.

    I would like to confirm what type of Ethernet PHY is connected to each external port and which silicon revision of AM335x is being used.

    It sounds like you have one port connected to an RGMII PHY and the other port connected to an RMII PHY.  Which PHY is connected to external ports 1 and 2?

    If you are using an RMII PHY on port 2, Usage Note 3.1.6 does not apply because the RMII2_CRS_DV signal function was added to the GPMC_A9 terminal.  If you are using silicon revision 1.0 with an RMII PHY on port 2, Usage Note 3.1.4 may apply if you are trying to use the same terminal for GPMC_WAIT0 and RMII2_CRS_DV.  If you are using any silicon revision with an MII PHY, the respective Usage Note (3.1.4 for silicon revision 1.0 and 3.1.6 for silicon revisions 2.x) applies if you are trying to use the same terminal for GPMC_WAIT0 and GMII2_CRS.

    TRM section 1.2.6 is describing an enhancement implemented in silicon revision 2.x, where a new pin multiplexing option was added for the GPMC_A9 terminal.  This is the difference between Usage Note 3.1.4 and Usage Note 3.1.6.  The enhancement eliminates the pin multiplexing limitation related to RMII, but not MII.

    If you are using an RMII PHY on port 2 there is an option to use the GPMC_A9 terminal for the RMII CRS_DV signal, so an external hardware solution will not be required.  If you are using an MII PHY on port 2, an external hardware solution will be required.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 805 points

    Thank you, with all answers and specially the last one, it is too much clear.

    "It sounds like you have one port connected to an RGMII PHY and the other port connected to an RMII PHY.  Which PHY is connected to external ports 1 and 2?"

    it is wright:
    RGMII -> port 1
    RMII -> port 2

    ..."and which silicon revision of AM335x is being used."

    We belive it is revision 2.0, printed on silicon surfare is:   "am3359zczd72     34a0gnw"

    But, I read the 0x44E10600 register from the silicon and got the value: 0xB94402E

    that value seems miss the last 28..31 bits that have revision value. Bellow is the used code in uboot -> function
     int board_eth_init(bd_t *bis)

    printf("\n------------>addr:%x \n", cdev);
    unsigned int val = readl(cdev);
    printf("\n------------>addr:%x val:%x \n", cdev, val);

    The same result was got with:

    unsigned int * addr = 0x44E10600;
    unsigned int val = readl(addr);
    printf("\n------------>addr:%x val:%x \n", cdev, val);

     

  • 0 in reply to daniel formolo
    TI__Guru 63155 points

    The device part number you provided indicates it is silicon revision 1.0, which requires an external multiplexer to share the GMPC_WAIT0 and RMII2_CRS_DV signal functions on the same terminal.

    Please refer to the Device Nomenclature figure in the AM335x data sheet.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 805 points

    ok Peaves, thank you again. That explain every thing.