MAX of DLL clock of AM437x ?

shigehiro tsuda

Hi,

I think that the following register is a register related to dll_clk of EMIF Clock Signals of Table 9-143 of TRM.

6.13.8.38 PRCM_CM_DIV_M4_DPLL_DDR Register

When read does a register after u-boot start, it turns out following.
0x44DF2DB8: 0x00000222
HSDIVIDER_CLKOUT1_DIV=0x2
Figure 6-288. PRCM_CM_CLKSEL_DPLL_DDR Register
0x44DF2DAC: 0x00003202
M=50,N=2
Figure 6-289. PRCM_CM_DIV_M2_DPLL_DDR Register
0x44DF2DB0: 0x00000221
M2 = 1
CLKINP=24MHz

It turns out following when I calculate in the calculating formula with mention in Table 6-17 Output Clocks in Locked Condition.
2 * [M / (N+1)] * CLKINP
DDR PLL DCOCLKLDO=2*[50/(2+1)] *24 = 800MHz

DDR PLL CLKOUTM4 = 800MHz/M4=800MHz/2=400MHz = dll_clk

In the case of M4=2, dll_clk exceeds 350MHz of MAX, do you not have any problem?
Is MAX 350MHz an error in writing?

Best Regards,

Shigehiro Tsuda

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

I will ask the DDR experts to check this. What software version are you using?

0 shigehiro tsuda over 10 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi Biser,

Thank you for your quick reply.
I use ti-processor-sdk-linux-am437x-evm-01.00.00.03 and ti-sdk-am437x-evm-08.00.00.00.
Both are same result.

Best Regards,
Shigehiro Tsuda

0 sivak over 9 years ago in reply to shigehiro tsuda

TI__Genius 9655 points

Where did you notice the max. of 350MHz on the DLL_CLK? The setting you've and the formula used appears to be correct.

Regards, Siva

0 Biser Gatchev-XID over 9 years ago in reply to sivak

TI__Guru**** 393215 points

I think he's referring to dll_clk in Table 9-143 EMIF Clock Signals in the AM437X TRM Rev. D

0 shigehiro tsuda over 9 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi,

Thank you for your reply.
Yes,I refer to dll_clk in Table 9-143 EMIF Clock Signals in the AM437X TRM Rev. D.
Here is mention that DLL_CLK is MAX350MHz.
Is mention of MAX 350MHz a mistake?

Best Regards,
Shigehiro Tsuda

0 JJD over 9 years ago in reply to shigehiro tsuda

TI__Guru* 85990 points

That is a typo. Max for dll_clk should be 400MHz. I will fix in the next release

Regards,
James

0 shigehiro tsuda over 9 years ago in reply to JJD

Mastermind 9490 points

Hi James,

Thank you for your reply.
I understand that TRM of AM437x is wrong and max dll_clk is 400MHz.
I'll talk with our customer.
I thank for your correspondence.

Best Regards,
Shigehiro Tsuda

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MAX of DLL clock of AM437x ?