Hi All,
I'm working on a design (OMAP3530) where we want to be able to boot directly from a standard async. NOR flash. (Not a multiplexed address/databus or sync burst type memory.) It seems that my schematic should work electrically, but I'm concerned about boot behaviour of the "XIP" sys_boot options. Has anyone done this successfully? Care to share what you did? [:)]
I haven't had much luck determining if there's any impact to the boot XIP option when using a standard async NOR with the external latch vs. another type of part? ie, will the OMAP automatically put the lower 16 address bits out on the GPMC_Dx bus during a cold boot without needing to "know" what type of NOR part you have hanging off the GPMC? (Or would the memory controller have to be programmed to do that? I'm a little fuzzy how/if the GPMC knows if there's async NOR vs. sync NOR vs. muxed data/address vs. not on the GPMC bus for the XIP boot memory...)
http://www.embeddedengineeringllc.com/OMAP/OMAP3530_NOR_Interface_Schem.GIF
Thanks,
-Clay
Clay Cowgill
Embedded Engineering, LLC
