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SRC4192: Input Clock Halting with Master Mode for Output Port

Sadanori Kato
Guru 36540 points
Part Number: SRC4192

Hi,

BCKO, LRCKO and SDOUT continue to be output even if BCKI, LRCKI and SDIN are asserted to low using SRC4192 with the master mode for the output port(e.g. : MODE2/MODE1/MODE0 = 0/1/1)
Moreover, the invalid data from SDOUT is outout continuously and /RDY pin remains low.
Is this behavior normal ?

Best regards,
Kato

  • 0
    TI__Expert 5645 points
    Hi Kato-san,
    I am looking into this query and will have an answer by Monday. Thanks.

    Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    TI__Expert 5645 points
    Hi Kato-san,
    The situation outlined where the Output data of SRC4192 is not always zero even if the input stream is zero is standard behavior for the SRC4192, and could be causing by dithering. The only options to work around it would be to use the bypass or mute.

    If you have a MCLKI to the part and no clocks in with the part set for Output Port as Master, then there will be BCKO & LRCKO clocks at the output.

    Best regards,
    Ravi
  • 0 in reply to Ravi Patil
    Guru 36540 points

    Hi Ravi-san,

    Thank you for your prompt reply.
    I understood.

    Best regards,
    Kato