SRC4392 register write

Hello,

In order to write to Register Page 2 and have your data stick, the DIT block must be powered up in register 0x01, Page 0, and the MCLK clock must be active. Internally, a clock is derived from MCLK to clock data from the serial host registers to the DIT block.

The following sequence should be used to initilaize the device.

1. Apply power and external reset.

2. Write all control registers on Page 0 except register 0x01.

3. Apply MCLK, as well as any audio clocks desired for Ports A and B.

4. Write register 0x01 on Page 0 to power up the desired blocks.

5. Disable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 1.

6. Write 0x02 to register 0x7F to set Page 2 as the active page.

7. Write data to the DIT C and U buffers on Page 2 as desired.

8. Write 0x00 to address 0x7F to set Page 0 as the active page.

9. Enable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 0. This will update the DIT TA buffer with the data written to Page 2 registers.

You can read back Page 2 registers without disabling buffer transfers. Just make sure to set the page register to Page 2. You should then be able to read back the buffer data.

Regards,

Bob Martin, Systems Engineering - TI Audio Converters

Thanks Bob!

Following your instructions got the transfer working and I was able to determine the cause of my problems:

cockpit error!

I was using RXCKO as the DIT clock and of course this doesn't start until the DIR first locks onto an incoming stream. After that the PLL can free run but as I was writing to the DIT before the stream was connected - no write!

Hello,

I have the very same problem as described by Iain McNeill: Writing to registers on page 2 does not  change the transmitted channel status nor can it be read back (just getting zeros).

Prerequisites:

I am only using Port A (Port B unconnected) in clock slave mode. An FPGA provides MCLK, sample clock and frame sync. I followed your steps without success so I asume an initialisation mistake. The sequence is as follows:

1. External reset

2. Setting control registers on page 0 (it's always register address first, then data [all values in hex])

Hi, Tobias,

I have tried your initialization and DIT buffer read and write for steps 5 - 9 on SRC4392 EVM. There is no problem for both read back and the transmission of the channel status data. Here is the script for steps 5 to 9:

w e0 08 08 - disable the DIT buffer transfer

w e0 7f 02 - set page to 2

w e0 2e ee - write ee to reg 2e on page 2

w e0 2f ff - write ff to reg 2f on page 2

w e0 7f 00 - change the page back to 0

w e0 08 00 - enable the DIT buffer transfer

w e0 7f 02 - switch back to page 2

r e0 2e 01 - read back reg 2e on page 2

r e0 2f 01 - read back reg 2f on page 2

w e0 7f 00 - set page to page 0

Before you send the commands for steps 5 -9, please check the DIT output to make sure that the DIT is already in operation.

Please let me know if you have further questions.

Regards,

Shawn Yu - System engineer

Hi Shawn,

thanks for your quick answer. I followed your instructions waiting for the DIT to come up (checking with another device locking onto the stream) and then issueing your write sequence. I still cannot see my channel status data coming up in the output stream nor am I able to read anything else than zeros on page 2.

The wierd thing is, when I set register 09 on page 0 to 02 I can read back status data from the input stream. This is working fine. Switching register 09 back to 01 and following steps 5-9 seems to reset the CU-buffer to zeros.

Am I missing something? What (other than the SPI init sequence) could lead to such behavior? Any help is appreciated.

Regards,

Tobias.

Hi, Tobias,

It sounds strange. Have you tried on any other SRC4392 devices? If not, please try the same and let me know if the problem still exists. Also send me the exact setup, write and readback sequences for me to check on the test bench.

Regards,

Shawn Yu