What is pin assignment of DAC34H84 to display four simple digital signals on oscilloscope?

Hi Nariman,

Besides the 32-bit wide LVDS data bus, you will need the DATACLK pair to clock in the data. For FIFO synchronization, you can simply use SIF_SYNC (software sync) to reduce the number of LVDS IOs. 

You can refer to page 43, data format section for more detail. 

We have a similar Altera Stratix code ready for the DAC3482. I can private message you to send to your email. You can simply duplicate the other 16-bit bus for the CD channels. 

-KH

Hi Kang Hsia,

I have not received any email from you regarding a Altera Stratix code for the DAC3482. Could you please send it to me? 

Thanks

Hi Kang Hsia,

Thanks for your file. Actually, in our Lab, everybody is working with VHDL and nobody knows anything about verilog. Unfortunately, your file is in verilog.

To be honest, we also bought the second DAC board from TI which is DAC34SH84 and we are interested in working with our new TI DAC boards. Could you please send me a VHDL design file for STRATIX IV (DE4SXG530KH40C2) associated with DAC34H84, if it is available?

Thanks for your attention

Nariman,

We currently do not have VHDL version of the firmware. However, most of the project consist of Altera Mega Function calls, and you can use the mega function settings to create the equivalent in your VHDL project. 

-KH

Hi Kang Hsia,

Actually, the project file you sent me cannot be compiled. Have you compiled it before? It gives me error.

Nariman,

The code has been compiled and successfully run on our TSW1400 EVM.

Can you elaborate on the error you're receiving? Can you copy it here?

Regards,
Matt Guibord

Hi Matt,

In the next posts, I will attached two figures that can show the Errors and problems.

In Fig. 1, you can clearly see the type of error I got when I compiled your file. Do you have any suggestion in this case to solve my problem?

Moreover, How do you get two 16 bit output signals from one 16 bit signal as an output signal defined in the entity?? because in the attached Fig.2  you can clearly see the negative pins for lvds_tx_port_p have not been defined and the pin assignments is unknown?

Apart from these Errors, I want to ask you two questions, How did you define differential pairs for output data pins (negative and positive)? and How did you get two 16 bit output signals from only one 16 bit output signal defined previously in the entity? Because after synthesis, you only have 16 bit in the pin planer for output signal and  negative output pines are not automatically appeared .

Finally, if you or your company like, I can send my design file (VHDL) as a test file for DAC34X associated with Altera Stratix IV after I will fix these errors.

Regards,

Nariman

Fig. 1

Fig. 2

Nariman,

I had seen that error when I tried to simulate it in Modelsim. You may be using an older version of Quartus (I had used 11.0). I think if you simply delete line 63 (hrbypass) in the file you have open in ALTDDIO_CLK_OUT.v it will work. I believe they had modified the function in the newer version of Quartus and the old version does not have the hrbypass parameter.

There shouldn't be any problems with the LVDS assignments. You only need to assign the positive pin and set it as LVDS and Quartus will assign the appropriate negative LVDS driver pin. When it compiles everything should be set correctly because that's when Quartus will go through and setup the negative pins.

If you get the VHDL finished, I wouldn't mind taking a look at it.

Regards,
Matt Guibord

Hi,

I have recently ordered DAC3484 EVM.

Can you send me the HDL (perferably VHDL, if not available then Verilog) code for any Xilinx FPGA interfacing.

I am interfacing the card to SP605 Xilinx kit.

Any suggestions will help me.

Hi,

You may refer to the following app note describing interfacing the DAC3482EVM with the Altera based FPGA.

http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa545&docCategoryId=1&familyId=2023

We currently do not have codes available for Xilinx platform.

-KH

Hi,

Then i have to start using Altera boards.

Can you send me the source code for TSW1400 card .

I am intending to add some additional HDL code along with TSW1400 driver code in the startix FPGA.

Hope it is allowed (as the board has got JTAG access). 

Hi Vasu,

The app note and the associated code are simplified version of the TSW1400 source code. We recommend that you start with this code as the original TSW1400 source code has many additional features that may complicate your design.

The code associated with the app note can be downloaded at:

http://www.ti.com/litv/zip/slaa545

Here is a post related to the compiling of the code that may help you:

http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/258436.aspx

-KH

Hi Kang,

Can you also send me the code for interfacing the DAC3482. I am going to use it for interfacing the DAC34H82 with ML605.

Thanks,

Michel

misko7@net.hr

Hi Ivan,

Unfortunately, we currently do not have codes for Xilinx based solution for the DAC348x family.

-Kang