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ADS5282 along with FMC-ADC adapter in spartan 6 device
I am using spartan 6 sp601 evaluation kit along with the FMC-ADC adapter(http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html)and ADS5282EVM(http://focus.ti.com/docs/toolsw/folders/print/ads5282evm.html) from texas instruments.i would like to write a vhdl code to control the LVDS DDR outputs provided from the ADS5282EVM to spartan 6 FMC pins.I am really confused about implementing the ddr logic in my custom ip..i connected my custom ip to a IPIF FIFO but seems that i missed data...Recently i read the xapp1064...Should i follow this way describing there in my design with FMC connector?Xapp 866 and 774 i thing that does not help when using the FMC pins...Am i right?Is anywhere a sample code in vhdl that capture LVDS DDR outputs ..I am using EDK 11.5...
thanx in advance
I had not seen the XAPP1064 before, but just took a quick glance at it. I am familiar with the XAPP866 and we do *not* implement the interface to the ADS5282 that way in our TSW1200. We found the use of the ISERDES and the DCM blocks to be overly complex and we found it difficult to get all the ISERDES needed for the 8 channels reset and synchronized together.
Attached is a sketch of how we implement the ADC to FPGA interface in our TSW1200. The TSW1200 uses a Virtex4, but i believe the Spartan6 should also have the IDELAY cells available.
The first thing that must be accomplished is getting the data latched into the FPGA using the DDR bit clock. The IDDR cell was used which simply latches the data on the rising edge and again on the falling edge. Then it ourputs the rising edge bit and the falling edge bit on the same clock edge. Since the DDR clock from the ADC is centered in the valid timing of the bit, and in the FPGA the clock must go through a clock buffer, there must be a way of making the data bit get to the IDDR cell at the right time to meet the setup and hold time of the IDDR cell. The IDELAY cell is used to delay the data to meet setup and hold times intot he IDDR.
Now the the serial data is latched into the FPGA correctly, the next step is to deserialize the data back down to the sample clock rate. To do this i build a shift register of flipflops after the IDDR cell until i have my 12 bits of sample data held in flipflops. Then at the right time i need to load those 12 bits of sample data into a parallel register to hold the deserialized sample. The way to determine when to load the data into the parallel register is to look at the FCLK or frame clock signal. I bring the frame clock into an IDDR cell just like it was another data channel. Don't be misled by the name of the signal as frame clock and try to use it as a clock right away; consider the frame clock to be a data bit with a known pattern so that you can look at the frame clock to see where the first bit of the sample data is when you deserialize the data. I look for the place in the frame clock pattern where the bit was low and next it was high to tell me when to make the signal to load the deserialized data in to the parallel data register. Only *then* do i take the frame clock signal from the IDDR cell and route it to a clock buffer to become the sample clock inside the FPGA to clock the deserialized data samples.
I find this to be the simplest and most robust way of getting the serial data from the ADS5282 into an FPGA, without the need for PLLs or DCMs or ISERDES.
Can i use this implementation, even though i do not use the TSW1200 but the FMC-ADC adapter module to connect the ADS5282EVM to my spartan 6 board?
Could you provide me with a vhdl code for this implementation?
Yes, you should be able to create code to make this implementation work once you connect the ADC EVM to the FPGA development platform through the adapter board.
We do not have VHDL code for this interface for the Spartan 6. You would have to create this interface. I do not have the details on the Spartan 6 development platform to know which IO pins on the Spartan will be connected to the various LVDS pairs from the ADS5282 EVM. The FMC-ADC adapter was developed for conencting the ADC EVM to the Virtex 6 development platform, and you would have to find our what pins on the Spartan 6 are connected to which LVDS pairs and define those pin assignments in your constraint file accordingly. One thing to watch out for in particular is to see what kind of IO pins the frame clock is connected to. On our revision B adapter board the frame clock went to a connector assignment that went to a clock-only input pin on the Virtex 6. For that reason we had to release a revision C adapter board that routed the frame clock to an FMC connector assignment that ultimately went to an input on the Virtex 6 that could also be used as a data input. I don't know which revision adapter board you have or what pins on the Spartan 6 will be connected to our EVM when you connect the three boards all together.
The frame clock is connected to the FMC M2C clock pair (CLK0_M2C_P/N) in the spartan 6 device..i have the revision B of FMC-ADC adapter module....
Will this cause problems to any implementation? And what problems?
I will be glad if you could provide me with your vhdl implementation for virtex4 or virtex 6 platforms to use it as samples for my design...
Can the CLK0_M2C_P/N input be used as a data pair input? That is, can this input to the FPGA be conencted to an IDDR cell so that the implementation that i described earlier could be implemented? If so then i think there woud be no problem. If the CLK0_M2C_P/N can only be connected to a clock tree inside the FPGA then i think you would have a problem to implement the circuitry that i described. In that case, i think you would prefer the revision C adapter board.
We did not create the TSW1200 FPGA firmware in VHDL. We used Verilog. We *do* upon request supply the Verilog source code of the TSW1200 with the understanding that it is not supported. The source code was not developed for public support and is to be taken as-is. Also, the source code is more complex than you would need it to be as the TSW1200 supports many more data formats than just the 1-wire 12-bit serial format of the ADS5282. I would need an email address to send the code to as well.
I dont know if it can be used as a data pair input since the manual of the board does not mention that kind of information...
i will try the implementation mention above and if it does not work i 'll try xilinx's one...
the only thing that i want to be sure is if xilinx implementation is suitable with my design (FMC-ADC adapter)...
my email is email@example.com
I have a similar setup and am trying to connect the ADC to a Virtex-6 device (ML605 board with FMC connector). I am still learning FPGA and having trouble to make it work. As you mentioned, the schemes from Xilinx App notes are complicated (to me). There is another document about connection the ADC to Lattice device, http://focus.ti.com/lit/ug/slau240/slau240.pdf. But the document is simple and the connector is totally different. Can you also send me a copy of the verilog code of TSW1200. My email is firstname.lastname@example.org Many thanks.
Information sent by email.
I am also looking for example interfacing code for the DAC5682EVM. Verilog code for the TSW1200 would be great; would it be possible to get a copy? My email is email@example.com. Do you make available any similar code for the TSW3070EVM or TSW3070EVM boards? Code for something like the TSW3100 would be perfect.
I just wanted to renew my request for code to the TSW1200, if possible.
The TSW1200 source code has been sent to the email address listed above.
I have a similar problem as other guys, and would appreciate it if you could send me the verilog source implementation of your ADC interface. I am trying to integrate an ADC 6445 EVK with my ML605 Xilinx board.
my email address is: firstname.lastname@example.org
Sent. I hope you find it useful.
I am looking for the verilog code of the TSW1200, can you send me a copy? My email is email@example.com.
I am also working on the deserialization of ADS6425 to virtex6(ml605). We are now trying both methods suggested by you and of our own. But still no progress yet for quite long time. May I have a copy of of the verilog code of TSW1200. My email is firstname.lastname@example.org . I am really appreciated for your help.
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