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ADS5282 along with FMC-ADC adapter in spartan 6 device

lefteris fysikopoulos
Intellectual 320 points
Other Parts Discussed in Thread: FMC-ADC-ADAPTER, ADS5282EVM, ADS5282, ADS6425, ADS5474, ADS5474EVM, ADS54RF63EVM, ADS54RF63, ADS5463, ADS5263EVM, ADS5263, AFE5851, AFE5801, ADS5273, AFE5801EVM, AFE5808

Hello,

I am using spartan 6 sp601 evaluation kit along with the FMC-ADC adapter(http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html)
and ADS5282EVM(http://focus.ti.com/docs/toolsw/folders/print/ads5282evm.html) from texas instruments.
i would like to write a vhdl code to control the LVDS DDR outputs provided from the ADS5282EVM to spartan 6 FMC pins.
I am really confused about implementing the ddr logic in my custom ip..
i connected my custom ip to a IPIF FIFO but seems that i missed data...
Recently i read the xapp1064...Should i follow this way describing there in my design with FMC connector?
Xapp 866 and 774 i thing that does not help when using the FMC pins...Am i right?
Is anywhere a sample code in vhdl that capture LVDS DDR outputs ..
I am using EDK 11.5...

thanx in advance

  • 0
    TI__Mastermind 29220 points

    Hi,

    I had not seen the XAPP1064 before, but just took a quick glance at it.  I am familiar with the XAPP866 and we do *not* implement the interface to the ADS5282 that way in our TSW1200.  We found the use of the ISERDES and the DCM blocks to be overly complex and we found it difficult to get all the ISERDES needed for the 8 channels reset and synchronized together.

    Attached is a sketch of how we implement the ADC to FPGA interface in our TSW1200.  The TSW1200 uses a Virtex4, but i believe the Spartan6 should also have the IDELAY cells available.

    The first thing that must be accomplished is getting the data latched into the FPGA using the DDR bit clock.  The IDDR cell was used which simply latches the data on the rising edge and again on the falling edge.  Then it ourputs the rising edge bit and the falling edge bit on the same clock edge.  Since the DDR clock from the ADC is centered in the valid timing of the bit, and in the FPGA the clock must go through a clock buffer, there must be a way of making the data bit get to the IDDR cell at the right time to meet the setup and hold time of the IDDR cell.  The IDELAY cell is used to delay the data to meet setup and hold times intot he IDDR.

    Now the the serial data is latched into the FPGA correctly, the next step is to deserialize the data back down to the sample clock rate.  To do this i build a shift register of flipflops after the IDDR cell until i have my 12 bits of sample data held in flipflops.  Then at the right time i need to load those 12 bits of sample data into a parallel register to hold the deserialized sample.  The way to determine when to load the data into the parallel register is to look at the FCLK or frame clock signal.  I bring the frame clock into an IDDR cell just like it was another data channel.  Don't be misled by the name of the signal as frame clock and try to use it as a clock right away; consider the frame clock to be a data bit with a known pattern so that you can look at the frame clock to see where the first bit of the sample data is when you deserialize the data.  I look for the place in the frame clock pattern where the bit was low and next it was high to tell me when to make the signal to load the deserialized data in to the parallel data register.  Only *then* do i take the frame clock signal from the IDDR cell and route it to a clock buffer to become the sample clock inside the FPGA to clock the deserialized data samples. 

    I find this to be the simplest and most robust way of getting the serial data from the ADS5282 into an FPGA, without the need for PLLs or DCMs or ISERDES.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    Hi Richard,

    Can i use this implementation, even though i do not use the TSW1200 but the FMC-ADC adapter module to connect the ADS5282EVM to my spartan 6 board?

    Could you provide me with a vhdl code for this implementation?

    Regards,

    Lefteris

  • 0 in reply to lefteris fysikopoulos
    TI__Mastermind 29220 points

    Yes, you should be able to create code to make this implementation work once you connect the ADC EVM to the FPGA development platform through the adapter board.

    We do not have VHDL code for this interface for the Spartan 6.   You would have to create this interface.  I do not have the details on the Spartan 6 development platform to know which IO pins on the Spartan will be connected to the various LVDS pairs from the ADS5282 EVM.   The FMC-ADC adapter was developed for conencting the ADC EVM to the Virtex 6 development platform, and you would have to find our what pins on the Spartan 6 are connected to which LVDS pairs and define those pin assignments in your constraint file accordingly.  One thing to watch out for in particular is to see what kind of IO pins the frame clock is connected to.  On our revision B adapter board the frame clock went to a connector assignment that went to a clock-only input pin on the Virtex 6.  For that reason we had to release a revision C adapter board that routed the frame clock to an FMC connector assignment that ultimately went to an input on the Virtex 6 that could also be used as a data input.  I don't know which revision adapter board you have or what pins on the Spartan 6 will be connected to our EVM when you connect the three boards all together.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    The frame clock is connected to the  FMC M2C clock pair (CLK0_M2C_P/N) in the spartan 6 device..i have the revision B of FMC-ADC adapter module....

    Will this cause problems to any implementation? And what problems?

    I will be glad if you could provide me with your vhdl implementation for virtex4 or virtex 6 platforms to use it as samples for my design...

    Regards,

    Lefteris

     

  • 0 in reply to lefteris fysikopoulos
    TI__Mastermind 29220 points

    Can the CLK0_M2C_P/N input be used as a data pair input?  That is, can this input to the FPGA be conencted to an IDDR cell so that the implementation that i described earlier could be implemented?  If so then i think there woud be no problem.  If the CLK0_M2C_P/N can only be connected to a clock tree inside the FPGA then i think you would have a problem to implement the circuitry that i described.  In that case, i think you would prefer the revision C adapter board.

    We did not create the TSW1200 FPGA firmware in VHDL.  We used Verilog.  We *do* upon request supply the Verilog source code of the TSW1200 with the understanding that it is not supported.  The source code was not developed for public support and is to be taken as-is.   Also, the source code is more complex than you would need it to be as the TSW1200 supports many more data formats than just the 1-wire 12-bit serial format of the ADS5282.  I would need an email address to send the code to as well.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    I dont know if it can be used as a data pair input since the manual of the board does not mention that kind of information...

    i will try the implementation mention above and if it does not work i 'll try xilinx's one...

    the only thing that i want to be sure is if xilinx implementation is suitable with my design (FMC-ADC adapter)...

    my email is lefteris.fysikopoulos@gmail.com

     

  • 0 in reply to Richard Prentice
    Prodigy 40 points

    Richard,

    I have a similar setup and am trying to connect the ADC to a Virtex-6 device (ML605 board with FMC connector). I am still learning FPGA and having trouble to make it work. As you mentioned, the schemes from Xilinx App notes are complicated (to me). There is another document about connection the ADC to Lattice device, http://focus.ti.com/lit/ug/slau240/slau240.pdf. But the document is simple and the connector is totally different.  Can you also send me a copy of the verilog code of TSW1200. My email is frank.li.pa@gmail.com Many thanks.

    Yan

  • 0 in reply to Frank Li50498
    TI__Mastermind 29220 points

    Information sent by email.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 70 points

     

    Richard,

    I am also looking for example interfacing code for the DAC5682EVM.  Verilog code for the TSW1200 would be great; would it be possible to get a copy?  My email is tristan.rocheleau@gmail.com.  Do you make available any similar code for the TSW3070EVM or TSW3070EVM boards?  Code for something like the TSW3100 would be perfect.

     

    Thanks,

    Tristan

     

     

     

  • 0 in reply to Richard Prentice
    Prodigy 70 points

    Richard,

    I just wanted to renew my request for code to the TSW1200, if possible.

     

    Thanks,

    Tristan

     

     

  • 0 in reply to Tristan Rocheleau
    TI__Mastermind 29220 points

    Hi,

    The TSW1200 source code has been sent to the email address listed above.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 110 points

    Hello Richard,

    I have a similar problem as other guys, and would appreciate it if you could send me the verilog source implementation of your ADC interface. I am trying to integrate an ADC 6445 EVK with my ML605 Xilinx board. 

    my email address is: hholisaz@gmail.com

    Thanks,

    Hamed H.

  • 0 in reply to Hamed Holisaz
    TI__Mastermind 29220 points

    Sent.  I hope you find it useful.

    Regards,

    Richard P.

  • 0
    Prodigy 30 points

    Richard,

    I am looking for the  verilog code of the TSW1200, can you send me a copy?  My email is yanhuipeng@163.com. 

     Thanks!

  • 0 in reply to Richard Prentice
    Prodigy 70 points

    Hi Richard,

    I am also working on the deserialization of ADS6425 to virtex6(ml605). We are now trying both methods suggested by you and of our own. But still no progress yet for quite long time. May I have a copy of of the verilog code of TSW1200. My email is turbot_yu@hotmail.com . I am really appreciated for your help.

    Alex

  • 0 in reply to Turbot
    Prodigy 10 points

    Hi Richard,

    I am new in here and i am working with ADS5474 / FMC-ADC-ADAPTER Rev. C / Spartan 6 SP605. This field is very difficult to me and i need some help. I saw that there is a sample implementation in verilog. It would be realy great if you can send me this. It would be a good way for me to understand more of this.

    My email is sssddd82@gmx.de 

    Is there any possibility to get a sample implementation in VHDL or a working IP Core to get the data out of the ADC?

    I am really appreciated for your help.

    SD 

  • 0 in reply to SD56370
    TI__Mastermind 29220 points

    sent to the address provided.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 10 points

    Hi Richard,

    Same like the others, I am conencting spartan-6 to ADS62P49EVM through the ADC FMC adapter. I will really appreciate it if you can send a copy of Verilog source code of the TSW1200 to:

    weeuiuc@gmail.com

    Thank you so much.

  • 0 in reply to wee chong
    TI__Mastermind 29220 points

    Sent to the address provided.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 10 points

    Hello Richard,

    I am using the ADS5282 with a Virtex-6.  May I please have a copy of the code you have been providing to others? My email address is joel.stan@gmail.com

    Thanks,

    Joel

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    Hi Richard,

    Spartan 6 has the IODELAY2 primitive instead of IDELAY. In FIXED mode is as using IDELAY primitive of VIRTEX 4.

    I would like to ask you if i can use the primitive in FIXED mode and what should be the fixed value of the delay for my adc(ADS5282EVM)?

    Regards,

    Lefteris

  • 0 in reply to lefteris fysikopoulos
    Prodigy 160 points

    Hello Richard,

    I will be interfacing the ADS5474EVM and ADS5282EVM to an Altera Cyclone III evaluation board. Please send me the Verilog code for the TSW1200EVM, as that could be a good reference. Send to seger@bridgerphotonics.com. Any other hints/references for interfacing TI ADC's to Altera FPGA's would also be helpful.

    Regards,

    Eric

  • 0 in reply to Eric Seger
    TI__Mastermind 29220 points

    sent by email.

    Regards,

    Richard P.

  • 0 in reply to lefteris fysikopoulos
    TI__Mastermind 29220 points

    hi,

    The TSW1200 used the IDELAY in an adjustable fashion because the TSW1200 has to support may devices.  We program the default setting of the IDELAY with a value that is suitable for a number of EVMs, and for other EVMs the TSW1200 User Interface will adjust the IDELAY settings dynamically.  Hence the VARIABLE mode for the IDELAY.

    If the IDELAY were to be used for meeting setup and hold timing for a single device family, then a fixed value would suffice.

    i can't tell you in advance what the proper value for the IDELAY in your FPGA will be.  In the TSW1200, each IDELAY tap setting is worth another 75ps of delay, but this will be different for different families of FPGA.  I don't know what the tap delay is for the Spartan.  Also, the number of tap setting needed will be such that the delay of the data through the IDELAY will match the delay of the clock through its IDELAY and clock buffering.  The clock buffering delay is different for each family, so that also makes for a different number of taps needed.

    There are two ways to determine the correct number of taps.  i use the timing analyzer in the Xilinx tools to determine what tap setting is needed to close the timing and then i use the other way to verify my work - that is, i increment or decrement the IDELAY tap setting until there bit errors in the data to see if my chosen tap setting is right in the middle of the range that is observed to work.

    To close timing, you will need a timing constraint in your ucf file that describes to the timing analyzer the setup and hold timing of the data from the ADC into the FPGA.  then the Static Timing analyzer in the mapping or place&route portion of the Xilinx tools will report if there are timing violations.  if there are timing violations for the ADC interface, the direction of the violation (either setup violation or hold violation) will tell you if you need more or less IDELAY, and the amount of the violation will tell you how many IDELAY tap settings you are away from meeting timing.  The timing constraint for a DDR input is the hardest portion of the job to get right, so you might wish to consult with Xilinx support if you need help with the syntax of that constraint.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 10 points

    Hi,

    Can you also send to ashefu_73@yahoo.com the deserialization code, please?

    thank you

     

  • 0 in reply to Aurel Stefu
    TI__Mastermind 29220 points

    Sent to the email address provided.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    I'm working on a custom s-6 design where several ads5281 are being used.

    To try out intermediate code I have ADS5282EVM, whichs has been succesfully connected to spartan 6 sp605 via FMC to ADC adapter adapting ideas and code from xapp866 & xapp774.

     

    however, i'd like to try out richard's approach, which seems much less demanding in terms of clock buffers.

    Richard, could you send me your code?

    My email is: pedro.guerra@upm.es

     

    has any one suceeded in implementing that in vhdl and setting the rigth ucf  constraints  for the S-6?.

    Some guidance with working constraints would be greatly appreciated.

     

     

     

     

     

  • 0 in reply to Pedro Guerra
    TI__Mastermind 29220 points

    sent to the address provided.

     

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 80 points

    Hi Richard,

    I am also looking for an alternative way to the Xilinx XAPPs, in this case for a ADC6445 to be connected to the ML605 board from Xilinx. Would you be s kind to share your verilog code with me, please?. Email address is gabriel.cutillas@silica.com.

    Thank a lot.

  • 0 in reply to Gabriel Cutillas
    TI__Mastermind 29220 points

    Sent to the address provided.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 85 points

    Hi - I also work with the ADS6424EVM and FMC-ADC-ADAPTER rev C on a SP605 board. I would also like to take a look on your deserialization code. baxter2002@hotmail.com

    many thx

  • 0 in reply to Richard Prentice
    Prodigy 40 points

    I'm also working on those boards, if you could send the example code to me as well that'd be great. email at hfjchan@triumf.ca.

    Thanks

  • 0 in reply to Justin Chan
    TI__Mastermind 29220 points

    Sent (for both requests) to the address provided.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 160 points

    Richard now, I also bought the boards.

    Can you send me the source code?

    My email is abysslover@gmail.com

  • 0 in reply to Lim Euncheon
    TI__Mastermind 29220 points

    Sent to the address provided.

    Also, since people do find these postings and append their request on to them, I'd like to suggest the following:  It may be safer to create a new posting to ask for the source code than to append a request on to an existing posting.  These posts are marked as 'verified' when the posting is resolved and appending a fresh request onto the posting does not re-mark them as 'open' or 'unresolved' cases again.  So if I don't catch the appended request when it is first put there, I may not know to respond later when I search the forum for unverified posts that need my attention.  And I may miss seeing the reuqest to answer it.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi,

     

    I would be very grateful if you could send me the VHDL implementation as well. Also, could you advise as to how easy/suitable it would be to try to use that as a starting point for writing firmware for an SP605 for data readout and processing from one of your ADS54RF63EVM boards? (I have the ADC/FMC adapter cards already)

     

    I am assuming that it would be better than nothing as a starting point but would be interested to hear what you think about whether this would be a useful thing to have when starting to write the firmware, and any advice you would give to a newbie trying to get off the ground!

     

    Many thanks.

     

    (email address: mmmerlin [at] hotmail [dot] com)

  • 0 in reply to Merlin Fisher-Levine
    TI__Mastermind 29220 points

    Sent to the address provided.

    As I mentioned in the email sent, the source code for the TSW1200 is much more complicated than it would otherwise need to be to just support one type of EVM such as the ADS54RF63.  The TSW1200 has to support so many different data formats that there are registers and multiplexors in the code to support the different choices, and state machines to support changing the IDELAY tap settings to support different timings for different device types.  For just a single ADC, much of the complexity could be stripped back out and some of the hierarchies of .v modules calling other .v modules could be flattened out.  Some of the complexity of the code is that the LVDS pin names form a bus of signals with one name assigned and lower levels of the code may use some of these pin assignments in different wyas to form yet other busses of signals - depending on whether the EVM is 1-channel or 2-channel or more. 

    So yes, this code contains a simple and robust interface from the ADC to the FPGA, if you can cut through all the layers of complexity in the HDL files.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Richard, could you send me your code?

    My email is: toomke@testron.ru

    Regards,

    Konstantin

  • 0 in reply to Konstantin Toom
    TI__Mastermind 29220 points

    Hi,

    What ADC would you want the code to work with?  You appended to a thread that has different devices mentioned.  The original posting was for an ADC that uses a serialized format, while the posting that you attached to was in reference to an ADC that uses a parallel LVDS format.

    The TSW1200 has *two* bit files stored in the eeprom: one for the serialized data format such as ADS5282 and the other for a parallel LVDS format such as ADS5463.  The Verilog code database is different for the two types, and i would need to know which type you are asking for.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi, Richard!
    I plan to use the ADS6425 which a serialized data format.
    Regards,
    Konstantin

  • 0 in reply to Richard Prentice
    Prodigy 80 points

    RIchard,

    I am using the ML605 and ADS5263EVM via the ADC-FMC-ADAPTER.  Can you please send the deserializer reference design to brabin@ofsoptics.com?

    Thank you,

    --Bryan

  • 0 in reply to Bryan Rabin
    TI__Mastermind 29220 points

    Hi,

    We do not have reference code for the ML605.   The code that we have been supplying upon request is Verilog source code for the TSW1200 which uses a Virtex4.  Also, the ADS5263 is not a product from the High Speed Data Converter group, but rather from our Medical and High Reliability Group.  The ADS5263EVM does not work with the TSW1200 anyway, but rather works with the TSW1250 from the Medical and Hirel Group.   If you post in the HiRel forum asking for TSW1250 Verilog code, they could send that to you. (and i will also send them an email pointing them to your request in this forum.)  But the code would have to be modified for use with the ML605 and FMC adapter.  They do not have ML605 example code either.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 210 points

    Hi,

    I'm using an AFE5851 EVM with a Xilinx Spartan 6 (SP605). I'm in trouble with the deserialization of the LVDS data.

    Could I have the vhdl code to do this operation? My email address is    rino.leombruno <at> gmail.com

    Thank you,

    RL

  • 0 in reply to Rino Leombruno
    TI__Mastermind 29220 points

    Hi,

    We do not have reference code for the SP605.   The code that we have been supplying upon request is Verilog source code for the TSW1200 which uses a Virtex4.  Also, the AFE5851 is not a product from the High Speed Data Converter group, but rather from our Medical and High Reliability Group.  The AFE5851 EVM does not work with the TSW1200 anyway, but rather works with the TSW1250 from the Medical and Hirel Group.   If you post in the HiRel forum asking for TSW1250 Verilog code, they could send that to you. (and i will also send them an email pointing them to your request in this forum.)  But the code would have to be modified for use with the SP605 and FMC adapter.  They do not have SP605 example code either.

    I am also attaching a sketch of how we chose to do the deserialization in the TSW1200 and TSW1250 using the Virtex4.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 85 points

    If this can help some I had a great success in deserializing an AFE5801 with a Spartan-6 by letting the major part of the work to the SelectIO Interface Wizard core. The remaining logic needed was the Bitslip state machine and the Gearbox logic as shown in the Xilinx xapp1064.

    Regards,

    Simon

  • 0 in reply to Simon Goyette
    Prodigy 210 points

    Thank you Richard and thank you Simon.

    I think that AFE5801 and AFE5851 are very similar and so I think your help could be very useful for me. I've just download the xapp1064 and i'm going to read that.

    Simon do you have some example code?

    Thank you very much for your help,

    RL

  • 0 in reply to Rino Leombruno
    Prodigy 85 points

    Here is the the code. This is a stripe down of my code with the guts of the deserializer part.

    5707.AFE5801Deserializer.zip

  • 0 in reply to Simon Goyette
    Prodigy 210 points

    Thank you so much Simon. Today I'm going to try to make the deserializer follow your aid. I have a question, how do you test your code before try it real?

    You are so courteous,

    thank you!

    RL

  • 0 in reply to Rino Leombruno
    Prodigy 210 points

    Sorry Simon, I have other question. What do you do with your sampled data? I have to save it in memory, i.e. 3500 samples for each channel in DDR3 RAM, and after that transfer it to the pc.

    Have you find how to do that? I ask  because i think that this is the most common and simple thing that one do with the sampled data.

    Thank you so much!

    RL

  • 0 in reply to Rino Leombruno
    Prodigy 85 points

    In simulation I used the Ads5273_Tester.vhd to feed the AFE5801 deserializer since the interface of the ADS5273 is similar. This testbench code is part of the xapp774.zip.

    The data is stored in a BRAM fifo (4000 samples) then transferred to a PC.