I have an application that requires projecting more than 96 1-bit frames at 4000Hz. I ideally I would be able to loop through at least 288 frames (3 x the current memory) or even do continuous update. It seems there are two main possibilities.
1) Increase the size of mDDR memory from 4 608x684 images to at least 12 images to accommodate more bit planes. Is the LightCrafter available with larger memory caches or is this difficult to switch out ourselves? Is there any reference for reprogramming the FPGA in this way?
2) Increase the speed of the 24bit RGB interface of the DLPC300 from 60Hz to 180Hz. This would allow arbitrarily long sequences at 4000Hz. Where is the bottleneck that limits this update speed? Is it on the DLPC300 or the the FPGA?
Standard graphics cards from Nvidia and ATI already support refresh rates of 180Hz or faster so it would be really cool if this projector kit could support these speeds as well. I would also be interested if we can just generate our own 4000Hz images using the embedded-Linux kernel and upload them to the DLPC300.
Are any of these options plausible as extensions to the standard LightCrafter kit?
Welcome to TI E2E Forum.
As already mentioned in the post here, it is not feasible to extend the mDDR memory above 4 24-bit images since it is used to store DMD system information.
Unfortunately, DLPC300 can only support up to 60Hz frame rate for Video mode and FPGA allows a maximum speed of 4000Hz for binary patterns.
I will investigate and update you on the possibility of loading patterns on the SD card and displaying the patterns at faster rate.
While it seems that there isn't any extra space in the existing 32MB (5MB of which is available for patterns), what I had in mind was physically switching out the FPGA memory chip for a larger chip. I understand that switching out IC components is not simple and may nore even be possible given the current hardware design. At the very least it would probably require reprogramming the FPGA.
However this is hard for me to judge without additional hardware information. While I could find specs for the DLPC300 mDDR memory on page 28 of the DLPC300 datasheet, I couldn't find any equivalent information for the FPGA.
Thanks for your quick response. I still remain excited about the possibility of transferring patterns from the SD card or main memory to the FPGA and am looking forward to these updates from TI.
You have to upgrade the firmware to be able to load more patterns through SD card. The software release might take 2 more weeks.I appreciate your patience.
For information on FPGA, these links might help- link & link.
Also, you should be aware that TI would not support the replacement of FPGA.
Has the new software been released yet? Will there be documentation of how to configure the LightCrafter to read pattern from the SD card?
The team is testing the beta version of the software and it should be released after the testing is complete. Yes, I will post the documentation on how to configure and use the software.
Thanks & Regards,
We are also reviewing an update to the DLPC300 SW Programmer's Guide that explains how the display sequences are configured through I2C commands. This will appear shortly.
Here is a little description of the DLPC300 video modes:
A DLP Display Sequence consists of several parameters which dictate the loading of the DMD and the control of PWM to the LEDs. To upload a Display Sequence, a Compound I2C command must be issue to read the sequence from SPI Flash firmware, load into DLPC300's processor memory, and configure the DLPC300's processor to this sequence. Section 2.2.9describes the Compound I2C command sequence.
Once a particular sequence is loaded into the DLPC300 processor memory, the Sequence Vector Setup selects the instance of the sequence to execute
DLPC300 supports two main video output modes: streaming data through the 24-bit RGB parallel bus or displaying previously loaded images from the DLPC300's mDDR Display Buffer. We call the first mode: External Video Sequence. While we call the pre-loaded images: Internal Pattern Sequence with Optional FPGA.
As shown in the attached, the DLPC300 stores four 24-bit frames in the mDDR. This portion of mDDR serves as the DLP3000 Display Buffer. The 96 bit-plane Display Buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces the oldest stored bit-plane. While the DLPC300 fills one buffer, the DLPC300 can read a previously filled buffer and load it into the DLP3000 DMD array. The DLPC300 takes 215 μs to load the first bit-plane into the DMD array. The DLPC300 takes135 μs to rotate buffers. Thus, for every 24-bit planes there is an additional 135 μs delay to rotate the buffer. These delays result in a maximum pattern rate of about 4 KHz per bit-plane.
The limit on bit-planes pre-loaded constrains the number of patterns in the internal video sequence mode. For external video streaming, there is no limit on number of patterns, but the maximum speed is dependent on the bit-depth and the frame rate.
External Video Sequence
The External Video Sequence supports 3-, 6-, 12-, 16-, 18-, or 24-bit RGB images, as well as, 1-, 2-, 3-, 4-, 5-, 6- ,7-, or 8-bit monochrome images at up to 60 Hz frame rate. These External Video Sequences take data streamed through the 24-bit RGB parallel bus at a pre-selected frame rate of 15, 30, 40/45, or 60 Hz. The 16-, 18-, and 24-bit External Video Sequences are typical of projection systems, while the 3-, 6-, and 12-bit RGB and the Monochrome Video Sequences are typically used in structure light applications.
Table 1 of the DLPC300 Data Sheets shows the external video sequences and and their maximum pattern rates.
Internal Video Sequence with Optional FPGA
The Internal Video Sequence supports 1-, 2-, 3-, 4-, 5-, 6- ,7, or 8-bit monochrome images. This mode utilizes custom Display Sequences with an optional FPGA to display monochrome patterns at higher speeds than the External Video Sequence. The DLPC300 in conjunction with an optional FPGA achieve higher speeds by pre-loading the images into the DLPC300's mDDR. Once the images are pre-loaded, the DLPC300 loads the images into the DMD while the FPGA rotates the Display buffer on every twenty-fourth bit-plane.
Table 2 of the DLPC300 Data Sheets shows the internal video sequences and and their maximum pattern rates.
However, the formula is wrong. The correct formula is:
In 1-bit internal video sequence mode, the DMD load is pipelined with the exposure time for the fastest rate possible.
Hopes this explains the operation of the DLPC300 and its pattern generation a little better.
Are the minimum exposure times listen in table 3-3 physical limitations of the system? I would have thought that 8 bit monochrome patterns could be displayed at 180Hz (based on 24-bit RGB display rate).
THe minimum exposure times is a limitation of the video sequences supported by the DLPC300. These video sequences take into account DMD load times. For 8-bit monochrome patters, that are streamed into the 24-bit RGB port, the maximum rate is 120 Hz. For 7-bit monochrome patterns streamed throughout the RGB port, the maximum rate is 180 Hz.
On the other hand, if the patterns are pre-loaded into the internal buffer, the maximum pattern rate for 8-bit monochrome is 115Hz. I a updating the DLPC300 SW Programmer's guide with descriptions on how to invoke these modes and will be released shortly.
Thank you for your post. I've got the following questions unclear:
1) In the formula for the pattern rate, "Pattern exposure period" should be the Number of Patterns multiplied by the exposure time for each pattern. Is that right?
2) The "Buffer rotate overhead" is 135 us x 4, or 135 us for each displayed pattern?
To be more specific, if I load 96 1bit images and set the exposure time to 250 us (the minimum allowed), does that mean that the whole set will be displayed for 96 x (250 us + 135 us) that is approximately 2597 Hz. If it is correct we cannot really achieve the 4 kHz refresh rate stated in the specification of the LCr.
Is there some period other than 135 us delay when making transition between the last and the first buffer, in case we are displaying over and over the same set of 96 images?
3) I tried to play a movie, consisting of 24-bit frames through the HDMI and wanted to display each of them as 24 1-bit frame (thus multiplying by 24 the 60 Hz refresh rate in video mode), but was unsuccessful. What do I get wrong?
4) Is there a possibility to skip loading the buffer. We need that, when continuous renewal of the 96-images set is required.
From what I was able to retrieve as information for the DLP 3000 chip, the internal interfaces between the SDRAM and DMD have transfer rate of 16 bit x 166 MHz (or 64 bit x 133 MHz). The time need to refresh the entire u-mirror array is 16 us (more than 60 kHz) that practically doesn't impose limitations. I am not an expert but if we are able to encode 16 1-bit images into single 16-bit frame, will that allow us to project at 16x166000/(684x608) > 6 kHz? If not why and how any limitation like this can be overcome.
1) The Pattern exposure period is the amount of time a single pattern is displayed. All patterns in a pattern sequence are exposed by the same amount of time.
2) The buffer rotate overhead is necessary when more than 24 bit planes are used. There are four buffers and each buffer can accommodate 24 bit planes. If the pattern sequence consumes more than 24 bit planes, then a buffer rotation is needed. Since all patterns have the same exposure time, then this buffer rotate penalty is added to all. Hence the formal has a difference between this pattern sequences that fit in 24 bit-planes or under and those that require more than 24 bit planes.
To achieve the 4KHz pattern rate, you can only create a pattern sequence with 24 1-bit images with a 250 us exposure time (this exposure time includes the bit plane load time). For greater than 24 1-bit images, then the pattern rate is 250 us + 135 us = 285 us or 2597 Hz.
3) You have to provide the 24-bit image with each 1-bit pattern serially shifted into each bit, as described in SW Programmers Guide Table 2-104 in Section 184.108.40.206.2.11. You also have to set LightCrafter using the GUI to HDMI video mode with 608 x 684.
4) The buffer is pre-loaded with the 96 images. Once preloaded, the only delay is the exposure time + buffer rotate overhead. The LightCrafter GUI always pre-loads the buffer with all the pattern images.
The limitations to the speed of the device have to do with DMD load times, sequences to control, resetting the mirrors, buffer rotate, etc. Also note that the DMD interface bus is only 15-bits at 76MHz and not 16-bit at 166 MHz. Thus, 4 KHz is the fastest pattern rate, if using 24 bit planes or less. 2597 Hz is the fastest pattern rate, if using more than 24 bit panes.
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