SRIO SerDes on 6678

Chris Thunes

I've been trying to modify the device_srio_loopback.c to run in non-loopback mode to test external loopback on the EVM6678 eval kit and am having some issues decoding the SerDes register values. The values in the code don't seem to match the definitions in the sprugw1 documentation. The lines from the file are

CSL_BootCfgSetSRIOSERDESConfigPLL (0x235);
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

Is there updated documentation for these?

Thanks,

Chris

over 14 years ago

0 jsobota over 14 years ago

TI__Intellectual 995 points

Chris,

Following are the changes you should make to switch to non-loopback mode. I'll try to find updated documentation for you.

The loopback settings are commented and replaced with non-loopback settings.

device_srio_loopback.c

int32_t SrioDevice_init(void)

{

...

    /* Configure SRIO to operate in loopback mode. */
//    CSL_SRIO_SetLoopbackMode(hSrio,0);
//    CSL_SRIO_SetLoopbackMode(hSrio,1);
//    CSL_SRIO_SetLoopbackMode(hSrio,2);
//    CSL_SRIO_SetLoopbackMode(hSrio,3);

    /* Configure SRIO to operate in normal mode. */
    CSL_SRIO_SetNormalMode(hSrio,0);
    CSL_SRIO_SetNormalMode(hSrio,1);
    CSL_SRIO_SetNormalMode(hSrio,2);
    CSL_SRIO_SetNormalMode(hSrio,3);

...

    /* Configure the SRIO SERDES Receive Configuration. */
    /* loopback mode */
// CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
// CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
// CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C40495);
// CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C40495);

    /* Non-loopback */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    /* loopback mode */
// CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);
// CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
// CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00780795);
// CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00780795);

    /* Non-loopback */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00180795);

...

}

Justin

0 Chris Thunes over 14 years ago in reply to jsobota

Intellectual 285 points

Thanks for the quick reply. That's what I have now actually, so I guess I'll start debugging the switch.

Thanks,

Chris

0 Chris Thunes over 14 years ago in reply to Chris Thunes

Intellectual 285 points

Hi,

I'm now trying to adjust the PLL multiplier in the example and running into the same issue with a mismatch between the documentation and example code. In particular, I think I'd like to set a multiplier of 5 for a data rate of 3.125 Gbps on the EVM boards, but I'm not sure if what's in the documentation is correct.

Thanks,

Chris

0 Chris Thunes over 14 years ago in reply to Chris Thunes

Intellectual 285 points

Also, any idea how soon updated documentation may be out for SRIO?

- Chris

0 jsobota over 14 years ago in reply to Chris Thunes

TI__Intellectual 995 points

Chris,

The UGs are continually revised and updated. I'm not sure when a new SRIO UG will be available so just continue to check back in the future.

Until then, you can use the following settings to configure the SRIO lane rates:

lane rate (Gbps)	SRIO_SERDES_CFGT/RX0-3 (Bits 4-5)	SRIO_SERDES_CFGPLL (Bits 0-9)
		ref_clock = 125 MHz	ref_clock = 156.25 MHz	ref_clock = 312.5 MHz
5	01 (half rate)	0x2A1	0x281	0x241
3.125	01 (half rate)	0x265	0x251	0x229
2.5	10 (quarter rate)	0x2A1	0x281	0x241
1.25	11 (eighth rate)	0x2A1	0x281	0x241

Justin

0 jsobota over 14 years ago in reply to jsobota

TI__Intellectual 995 points

The last column got cut off...

it should read:

ref_clock = 312.5 MHz

0x241

0x229

0x241

0 Chris Thunes over 14 years ago in reply to jsobota

Intellectual 285 points

Thanks Justin, I'll give that a shot and see how it goes. The loopback example code for the 6678 uses a value of 0x235. Do you know what this value corresponds to?

Thanks,

Chris

0 jsobota over 14 years ago in reply to Chris Thunes

TI__Intellectual 995 points

That's an old value used during silicon bringup. It may be unstable now. Use any of the values specified in the table.

Justin

0 simon64 over 14 years ago in reply to jsobota

Prodigy 120 points

Justin,

We have run into the same problem, which your post on 6th June has partially solved - many thanks.

With reference to you post on 14th of June, how do we configure the SRIO lane rates? Can this be done from the software running on the DSP?

Simon

0 tscheck over 14 years ago in reply to simon64

TI__Mastermind 23525 points

Simon,

Yes the Serdes configuration sets the lane rates and is set by DSP software, or the bootROM if you are using SRIO boot. Please take a look at this thread:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/127613/463219.aspx#463219

Regards,

Travis

0 simon64 over 14 years ago in reply to tscheck

Prodigy 120 points

Another question with reference to the table in the post on Jun 14 2011 4:15 PM, we would like to use the 1.25 GBps 'eighth rate' lane rate, however table 2-12 in sprugw1.pdf states that setting bits 4 and 5 to '11' (corresponding to eighth rate) is reserved.

Please can you confirm if eighth rate is supported by the device?

0 tscheck over 14 years ago in reply to simon64

TI__Mastermind 23525 points

Simon,

That is a known error in the user guide. There should be a new revision published soon.

Regards,

Travis

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SRIO SerDes on 6678