C667x EMIF 16

Hector Rivera said:

What is the EMIF 16 data rate?  He is looking for an estimate wiht the processor runing at 1GHz.  He think that the maximum rate for a C^^7x running at 1 GHz would be 888Mbit/sec.  Is this calculation correct?

Based on SPRUGZ3a http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf it looks like the EMIF 16 only supports asynchronous accesses, so a minimum transfer time would be a setup, strobe and hold cycle of at least one clock so there would be three clocks for each data access in the best case. The clock speed for EMIF 16 looks to be CPU/6 so 166.6 MHz for a 1 GHz setup. If you take 166.6 / 3 for the setup/strobe/hold the effective data rate on the interface should be 55.53 M words/sec, which would correlate to 55.53 * 16 for a 16 bit wide bus for 888 Mbit/sec as you have calculated, so I for one agree with your figure unless there are some limitations I have not come across. 

Bernie is correct. The transfer time depends on the programmed setup/strobe/hold timings which in turn depend on the memory device used.

As stated, EMIF16 will operate at 166.6MHz when cpuF = 1GHz. For example, if your async memory device allows you to have setup/strobe/hold = 2/4/2 for writes and 2/6/2 for reads, you could achieve a theoretical data rate of 300Mbps for writes and 240Mbps for reads. The reason I mention theoretical is because you can expect contention due to other masters as well the read-write turnaround time.

Hector,

Since you mentioned the customer is connecting EMIF16 to FPGA:

There is an unused internal feature in the EMIF16 that was uncovered, that can cause unintended delays between some EMIF16 accessesand degrade EMIF16 throughput. TI recommends disabling this feature for all applications that make use of EMIF16.  The feature can be disabled by setting the msb of 0x20C00008 to 1. It is recommended to do this setting before configuring any aspect of the EMIF16 peripheral.

*(Uint32*)0x20C00008 |= 0x80000000;  // Disable unused internal EMIF feature

   How about of DM368 connect to FPGA at EMIF16,the internal clock is 170M,setup,strobe and hold are minus.But I find it using 6 clock cycle everytime.

Branty, I am not sure whether the EMIF16 in DM368 uses the same IP as C66x DSPs. You might want to post your question in the DM3x processors forum: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100.aspx