Booting from NOR on EVM6678L (Image Processing Demo)

Hi Hideo,

The GEL initializes DDR ctrl registers. The DDR will be un-reliable if the GEL is not run in when board is booted in no-boot mode. I will update the user guide with this information.

Are you seeing issue while writing the image to NOR?

Regards

Sajesh

ATTENTION!!! 

 

This is looooong message.

 

 

Hello Sajesh,

 

Yes, it seems flashing NOR is successful.

 

I've read the updated document (MCSDK Image Processing Demonstration Guide).

But not in sucess.

 

 

 

The steps I did (and the messages in CCS console window) follow :

 

<MCSDK INSTALL DIR> is MCSDK 2.00.04.16 install directory.

In my case, it is 'C:\Program Files\Texas Instruments\mcsdk_2_00_04_16'

 

---------------------------

- Write IBL configuration -

---------------------------

  0. Change IBL configuration in <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cConfig.gel as mentioned in above document.

       - change norBoot.bootFormat as 'ibl_BOOT_FORMAT_BBLOB'

       - change norBoot.blob[0][0].startAddress as '0x9e000000'

       - change norBoot.blob[0][0].branchAddress as '0x9e001040'

  1. Power on the JTAG emulator 560v2, then power on the EVM,

     open CCS, load the target, and load evm6678l.gel on core 0.

 

//// messages in CCS console window follow

C66xx_0: GEL Output: Setup_Memory_Map...

C66xx_0: GEL Output: Setup_Memory_Map... Done.

 

  2. Connect to core 0

 

//// messages in CCS console window follow

C66xx_0: GEL Output: 

Connecting Target...

C66xx_0: GEL Output: DSP core #0

C66xx_0: GEL Output: C6678L GEL file Ver is 1.5 

C66xx_0: GEL Output: Setup Cache... 

C66xx_0: GEL Output: L1P = 32K   

C66xx_0: GEL Output: L1D = 32K   

C66xx_0: GEL Output: L2 = ALL SRAM   

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: PLL1 Setup... 

C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 

C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

C66xx_0: GEL Output: PA PLL is using SYSCLK/ALTCORECLK as the input

C66xx_0: GEL Output: PA PLL is in PLL mode

C66xx_0: GEL Output: PA PLL fixed output divider = 2

C66xx_0: GEL Output: PA PLL programmable multiplier = 21

C66xx_0: GEL Output: PA PLL programmable divider = 1

C66xx_0: GEL Output: the output frequency should be 10 times the PA reference clock

C66xx_0: GEL Output: configSGMIISerdes Setup... Begin

C66xx_0: GEL Output: 

SGMII SERDES has been configured.

C66xx_0: GEL Output: Enabling EDC ...

C66xx_0: GEL Output: L1P error detection logic is enabled.

C66xx_0: GEL Output: L2 error detection/correction logic is enabled.

C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.

C66xx_0: GEL Output: Enabling EDC ...Done 

C66xx_0: GEL Output: Configuring CPSW ...

C66xx_0: GEL Output: Configuring CPSW ...Done 

C66xx_0: GEL Output: DDR begin (1333 auto)

C66xx_0: GEL Output: XMC Setup ... Done 

C66xx_0: GEL Output: 

DDR3 initialization is complete.

C66xx_0: GEL Output: DDR done

 

  3. Load i2cConfig.gel in <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin on core 0.

 

  4. Load I2C writer <MCSDK INSTALL DIR>\tools\boot_loader\ibl\src\make\bin\i2cparam_0x51_c6678_le_0x500.out to core 0.

 

//// messages in CCS console window follow

C66xx_0: GEL Output: Invalidate All Cache...

C66xx_0: GEL Output: Invalidate All Cache... Done.

C66xx_0: GEL Output: DSP Reset CPU...

C66xx_0: GEL Output: DSP Reset CPU... Done.

C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.

 

  5. Push 'Resume' button to run.

 

//// message in CCS console window follows

[C66xx_0] Run the GEL for for the device to be configured, press return to program the I2C

 

  6. Run the GEL script 'EVM c6678 IBL' -> 'setConfig_c6678_main'

 

//// no messages produced in CCS console window

 

  7. Hit enter on CCS console window.

     -> Core 0 stopped at 'abort() at exit.c:99'

 

//// message in CCS console window follows

[C66xx_0] I2c table write complete

 

  8. Push 'Terminate' button to disconnect the target, then power off the EVM and JTAG emulator, close CCS.

 

-------------------

- Write NOR image -

-------------------

  9. Copy <MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evm6678l\images\mcip-c6678-le.bin to <MCSDK INSTALL DIR>\tools\writer\nor\evmc6678l\bin\app.bin

 

 10. Power on the JTAG emulator 560v2, then power on the EVM, then open CCS, load the target, and load evm6678l.evm on core 0.

 

//// messages in CCS console window follow:

C66xx_0: GEL Output: Setup_Memory_Map...

C66xx_0: GEL Output: Setup_Memory_Map... Done.

 

 11. Connect to core 0

 

//// messages in CCS console window follow:

C66xx_0: GEL Output: 

Connecting Target...

C66xx_0: GEL Output: DSP core #0

C66xx_0: GEL Output: C6678L GEL file Ver is 1.5 

C66xx_0: GEL Output: Setup Cache... 

C66xx_0: GEL Output: L1P = 32K   

C66xx_0: GEL Output: L1D = 32K   

C66xx_0: GEL Output: L2 = ALL SRAM   

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: PLL1 Setup... 

C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 

C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

C66xx_0: GEL Output: PA PLL is using SYSCLK/ALTCORECLK as the input

C66xx_0: GEL Output: PA PLL is in PLL mode

C66xx_0: GEL Output: PA PLL fixed output divider = 2

C66xx_0: GEL Output: PA PLL programmable multiplier = 21

C66xx_0: GEL Output: PA PLL programmable divider = 1

C66xx_0: GEL Output: the output frequency should be 10 times the PA reference clock

C66xx_0: GEL Output: configSGMIISerdes Setup... Begin

C66xx_0: GEL Output: 

SGMII SERDES has been configured.

C66xx_0: GEL Output: Enabling EDC ...

C66xx_0: GEL Output: L1P error detection logic is enabled.

C66xx_0: GEL Output: L2 error detection/correction logic is enabled.

C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.

C66xx_0: GEL Output: Enabling EDC ...Done 

C66xx_0: GEL Output: Configuring CPSW ...

C66xx_0: GEL Output: Configuring CPSW ...Done 

C66xx_0: GEL Output: DDR begin (1333 auto)

C66xx_0: GEL Output: XMC Setup ... Done 

C66xx_0: GEL Output: 

DDR3 initialization is complete.

C66xx_0: GEL Output: DDR done

 

 12. Load <MCSDK INSTALL DIR>\tools\writer\nor\evm6678l\bin\norwriter_evm6678l.out on core 0.

 

//// messages in CCS console window follow:

C66xx_0: GEL Output: Invalidate All Cache...

C66xx_0: GEL Output: Invalidate All Cache... Done.

C66xx_0: GEL Output: DSP Reset CPU...

C66xx_0: GEL Output: DSP Reset CPU... Done.

C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.

 

 13. Open 'Memory Browser' window and enter '0x9e000000' in the text box and hit 'Go'

     -> 'Hex 32 Bit - TI Style' and show the memory contents starting at 0x9E000000.

 

 14. Right click on the window, and select 'Load Memory...'

     -> 'Load Memory' dialog shows up.

 

 15. Enter '<MCSDK INSTALL DIR>\demos\image_processing\utils\mad\evmc6678l\images\mcip-c6678-le.bin' in the 'File:' text box and push 'Next >'

     -> the dialog says 'Format: Raw Data' and the target's length is '0x112000'

 

 16. Enter 'Start Address:' as '0x9e000000' and set 'Type-size:' is '8 bits' and 'swap' checkbox is UNchecked, then push 'Finish'.

     -> after some seconds, most of the memory contents turns RED that indicates the data has changed.

 

 17. Hit 'Resume' button to run for NOR writer to write the image.

     -> Core 0 stopped at 'abort() at exit.c:99'

 

//// messages in CCS console window follow:

[C66xx_0] NOR Writer Utility Version 01.00.00.03

[C66xx_0] 

[C66xx_0] Flashing sector 0 (0 bytes of 4489216)

[C66xx_0] Flashing sector 1 (65536 bytes of 4489216)

[C66xx_0] Flashing sector 2 (131072 bytes of 4489216)

[C66xx_0] Flashing sector 3 (196608 bytes of 4489216)

[C66xx_0] Flashing sector 4 (262144 bytes of 4489216)

[C66xx_0] Flashing sector 5 (327680 bytes of 4489216)

[C66xx_0] Flashing sector 6 (393216 bytes of 4489216)

[C66xx_0] Flashing sector 7 (458752 bytes of 4489216)

[C66xx_0] Flashing sector 8 (524288 bytes of 4489216)

[C66xx_0] Flashing sector 9 (589824 bytes of 4489216)

[C66xx_0] Flashing sector 10 (655360 bytes of 4489216)

[C66xx_0] Flashing sector 11 (720896 bytes of 4489216)

[C66xx_0] Flashing sector 12 (786432 bytes of 4489216)

[C66xx_0] Flashing sector 13 (851968 bytes of 4489216)

[C66xx_0] Flashing sector 14 (917504 bytes of 4489216)

[C66xx_0] Flashing sector 15 (983040 bytes of 4489216)

[C66xx_0] Flashing sector 16 (1048576 bytes of 4489216)

[C66xx_0] Flashing sector 17 (1114112 bytes of 4489216)

[C66xx_0] Flashing sector 18 (1179648 bytes of 4489216)

[C66xx_0] Flashing sector 19 (1245184 bytes of 4489216)

[C66xx_0] Flashing sector 20 (1310720 bytes of 4489216)

[C66xx_0] Flashing sector 21 (1376256 bytes of 4489216)

[C66xx_0] Flashing sector 22 (1441792 bytes of 4489216)

[C66xx_0] Flashing sector 23 (1507328 bytes of 4489216)

[C66xx_0] Flashing sector 24 (1572864 bytes of 4489216)

[C66xx_0] Flashing sector 25 (1638400 bytes of 4489216)

[C66xx_0] Flashing sector 26 (1703936 bytes of 4489216)

[C66xx_0] Flashing sector 27 (1769472 bytes of 4489216)

[C66xx_0] Flashing sector 28 (1835008 bytes of 4489216)

[C66xx_0] Flashing sector 29 (1900544 bytes of 4489216)

[C66xx_0] Flashing sector 30 (1966080 bytes of 4489216)

[C66xx_0] Flashing sector 31 (2031616 bytes of 4489216)

[C66xx_0] Flashing sector 32 (2097152 bytes of 4489216)

[C66xx_0] Flashing sector 33 (2162688 bytes of 4489216)

[C66xx_0] Flashing sector 34 (2228224 bytes of 4489216)

[C66xx_0] Flashing sector 35 (2293760 bytes of 4489216)

[C66xx_0] Flashing sector 36 (2359296 bytes of 4489216)

[C66xx_0] Flashing sector 37 (2424832 bytes of 4489216)

[C66xx_0] Flashing sector 38 (2490368 bytes of 4489216)

[C66xx_0] Flashing sector 39 (2555904 bytes of 4489216)

[C66xx_0] Flashing sector 40 (2621440 bytes of 4489216)

[C66xx_0] Flashing sector 41 (2686976 bytes of 4489216)

[C66xx_0] Flashing sector 42 (2752512 bytes of 4489216)

[C66xx_0] Flashing sector 43 (2818048 bytes of 4489216)

[C66xx_0] Flashing sector 44 (2883584 bytes of 4489216)

[C66xx_0] Flashing sector 45 (2949120 bytes of 4489216)

[C66xx_0] Flashing sector 46 (3014656 bytes of 4489216)

[C66xx_0] Flashing sector 47 (3080192 bytes of 4489216)

[C66xx_0] Flashing sector 48 (3145728 bytes of 4489216)

[C66xx_0] Flashing sector 49 (3211264 bytes of 4489216)

[C66xx_0] Flashing sector 50 (3276800 bytes of 4489216)

[C66xx_0] Flashing sector 51 (3342336 bytes of 4489216)

[C66xx_0] Flashing sector 52 (3407872 bytes of 4489216)

[C66xx_0] Flashing sector 53 (3473408 bytes of 4489216)

[C66xx_0] Flashing sector 54 (3538944 bytes of 4489216)

[C66xx_0] Flashing sector 55 (3604480 bytes of 4489216)

[C66xx_0] Flashing sector 56 (3670016 bytes of 4489216)

[C66xx_0] Flashing sector 57 (3735552 bytes of 4489216)

[C66xx_0] Flashing sector 58 (3801088 bytes of 4489216)

[C66xx_0] Flashing sector 59 (3866624 bytes of 4489216)

[C66xx_0] Flashing sector 60 (3932160 bytes of 4489216)

[C66xx_0] Flashing sector 61 (3997696 bytes of 4489216)

[C66xx_0] Flashing sector 62 (4063232 bytes of 4489216)

[C66xx_0] Flashing sector 63 (4128768 bytes of 4489216)

[C66xx_0] Flashing sector 64 (4194304 bytes of 4489216)

[C66xx_0] Flashing sector 65 (4259840 bytes of 4489216)

[C66xx_0] Flashing sector 66 (4325376 bytes of 4489216)

[C66xx_0] Flashing sector 67 (4390912 bytes of 4489216)

[C66xx_0] Flashing sector 68 (4456448 bytes of 4489216)

[C66xx_0] Reading and verifying sector 0 (0 bytes of 4489216)

[C66xx_0] Reading and verifying sector 1 (65536 bytes of 4489216)

[C66xx_0] Reading and verifying sector 2 (131072 bytes of 4489216)

[C66xx_0] Reading and verifying sector 3 (196608 bytes of 4489216)

[C66xx_0] Reading and verifying sector 4 (262144 bytes of 4489216)

[C66xx_0] Reading and verifying sector 5 (327680 bytes of 4489216)

[C66xx_0] Reading and verifying sector 6 (393216 bytes of 4489216)

[C66xx_0] Reading and verifying sector 7 (458752 bytes of 4489216)

[C66xx_0] Reading and verifying sector 8 (524288 bytes of 4489216)

[C66xx_0] Reading and verifying sector 9 (589824 bytes of 4489216)

[C66xx_0] Reading and verifying sector 10 (655360 bytes of 4489216)

[C66xx_0] Reading and verifying sector 11 (720896 bytes of 4489216)

[C66xx_0] Reading and verifying sector 12 (786432 bytes of 4489216)

[C66xx_0] Reading and verifying sector 13 (851968 bytes of 4489216)

[C66xx_0] Reading and verifying sector 14 (917504 bytes of 4489216)

[C66xx_0] Reading and verifying sector 15 (983040 bytes of 4489216)

[C66xx_0] Reading and verifying sector 16 (1048576 bytes of 4489216)

[C66xx_0] Reading and verifying sector 17 (1114112 bytes of 4489216)

[C66xx_0] Reading and verifying sector 18 (1179648 bytes of 4489216)

[C66xx_0] Reading and verifying sector 19 (1245184 bytes of 4489216)

[C66xx_0] Reading and verifying sector 20 (1310720 bytes of 4489216)

[C66xx_0] Reading and verifying sector 21 (1376256 bytes of 4489216)

[C66xx_0] Reading and verifying sector 22 (1441792 bytes of 4489216)

[C66xx_0] Reading and verifying sector 23 (1507328 bytes of 4489216)

[C66xx_0] Reading and verifying sector 24 (1572864 bytes of 4489216)

[C66xx_0] Reading and verifying sector 25 (1638400 bytes of 4489216)

[C66xx_0] Reading and verifying sector 26 (1703936 bytes of 4489216)

[C66xx_0] Reading and verifying sector 27 (1769472 bytes of 4489216)

[C66xx_0] Reading and verifying sector 28 (1835008 bytes of 4489216)

[C66xx_0] Reading and verifying sector 29 (1900544 bytes of 4489216)

[C66xx_0] Reading and verifying sector 30 (1966080 bytes of 4489216)

[C66xx_0] Reading and verifying sector 31 (2031616 bytes of 4489216)

[C66xx_0] Reading and verifying sector 32 (2097152 bytes of 4489216)

[C66xx_0] Reading and verifying sector 33 (2162688 bytes of 4489216)

[C66xx_0] Reading and verifying sector 34 (2228224 bytes of 4489216)

[C66xx_0] Reading and verifying sector 35 (2293760 bytes of 4489216)

[C66xx_0] Reading and verifying sector 36 (2359296 bytes of 4489216)

[C66xx_0] Reading and verifying sector 37 (2424832 bytes of 4489216)

[C66xx_0] Reading and verifying sector 38 (2490368 bytes of 4489216)

[C66xx_0] Reading and verifying sector 39 (2555904 bytes of 4489216)

[C66xx_0] Reading and verifying sector 40 (2621440 bytes of 4489216)

[C66xx_0] Reading and verifying sector 41 (2686976 bytes of 4489216)

[C66xx_0] Reading and verifying sector 42 (2752512 bytes of 4489216)

[C66xx_0] Reading and verifying sector 43 (2818048 bytes of 4489216)

[C66xx_0] Reading and verifying sector 44 (2883584 bytes of 4489216)

[C66xx_0] Reading and verifying sector 45 (2949120 bytes of 4489216)

[C66xx_0] Reading and verifying sector 46 (3014656 bytes of 4489216)

[C66xx_0] Reading and verifying sector 47 (3080192 bytes of 4489216)

[C66xx_0] Reading and verifying sector 48 (3145728 bytes of 4489216)

[C66xx_0] Reading and verifying sector 49 (3211264 bytes of 4489216)

[C66xx_0] Reading and verifying sector 50 (3276800 bytes of 4489216)

[C66xx_0] Reading and verifying sector 51 (3342336 bytes of 4489216)

[C66xx_0] Reading and verifying sector 52 (3407872 bytes of 4489216)

[C66xx_0] Reading and verifying sector 53 (3473408 bytes of 4489216)

[C66xx_0] Reading and verifying sector 54 (3538944 bytes of 4489216)

[C66xx_0] Reading and verifying sector 55 (3604480 bytes of 4489216)

[C66xx_0] Reading and verifying sector 56 (3670016 bytes of 4489216)

[C66xx_0] Reading and verifying sector 57 (3735552 bytes of 4489216)

[C66xx_0] Reading and verifying sector 58 (3801088 bytes of 4489216)

[C66xx_0] Reading and verifying sector 59 (3866624 bytes of 4489216)

[C66xx_0] Reading and verifying sector 60 (3932160 bytes of 4489216)

[C66xx_0] Reading and verifying sector 61 (3997696 bytes of 4489216)

[C66xx_0] Reading and verifying sector 62 (4063232 bytes of 4489216)

[C66xx_0] Reading and verifying sector 63 (4128768 bytes of 4489216)

[C66xx_0] Reading and verifying sector 64 (4194304 bytes of 4489216)

[C66xx_0] Reading and verifying sector 65 (4259840 bytes of 4489216)

[C66xx_0] Reading and verifying sector 66 (4325376 bytes of 4489216)

[C66xx_0] Reading and verifying sector 67 (4390912 bytes of 4489216)

[C66xx_0] Reading and verifying sector 68 (4456448 bytes of 4489216)

[C66xx_0] NOR programming completed successfully

 

 18. Push 'Terminate' button to disconnect the target, then power off the EVM and JTAG emulator, close CCS.

 

-----------------

- Boot from NOR -

-----------------

 19. Set the EVM dip switchs to boot from NOR (NOR boot on image 0) as specified in the hardware setup table (TMDXEVM6678L)

 

 20. Power on the EVM!

     -> nothing happened..., cannot respond ping command, connect via http from a web browser...

 

That's all I did.

Anything wrong???

 

Sorry for long message.

 

Best Regards,

Hideo

Sajesh Kumar Saran said:

Hi Hideo,

The GEL initializes DDR ctrl registers. The DDR will be un-reliable if the GEL is not run in when board is booted in no-boot mode. I will update the user guide with this information.

Are you seeing issue while writing the image to NOR?

Regards

Sajesh

 

Hi Hideo,

You are using BIOS MCSDK version 2.0.4, so you should use 0x8* for the addresses, 0x9e* is for 2.0.5+ version of BIOS MCSDK release.

Could you please try it out with corrected addresses and let us know if you are still seeing the issue?

Regards

Sajesh

Hi Sajesh,

I have the same problem on MCSDK 2.0.5.

I have follow this page : http://processors.wiki.ti.com/index.php/MCSDK_Image_Processing_Demonstration_Guide#Booting_from_NOR

No error during the process. But nothing on UART during boot (The UART is OK), and no ping or other access.

We have to put the app on 0x80000000 adress, according to the Wiki. Even with MCSDK 2.0.5 ?

Thanking you in advance  

 

EDIT : I have try the i2cnorboot example, with the inital i2c gel file, and it doesn't work too.

Hi,

I have try  this : Loading and running MAD linked image using CCS from the MAD guide (http://processors.wiki.ti.com/index.php/MAD_Utils_User_Guide). But, on no-boot mode, when I follow thoses intructions, nothing happen too (UART or CCS).

And with Nor boot, when I looking Memory Map around 0x9e000000, I can see the same than when I am loading the program trough CCS.

I use to pre-build mcip-c6678-le.bin file provide with mcsdk (Version 2_00_05_17)

 

Thanking you in advance