PCIe Documentation problem MSI registers

Mark Swick

In document number SPRUGS6A, SECTION 3.6 puts the MSI registers in the same addresses as the IRQ_EOI and the MSI_IRQ registers.

Is this a typo?

What is the purpose of the MSI registers of SECTION 3.6?

over 13 years ago

0 Steven Ji over 13 years ago

TI__Genius 12065 points

Mark,

Please refer to the section 2.7 PCIe Address Space, especially Figure 2-6 and Table 2-7, in the same document.

IRQ_EOI and MSI_IRQ are Application Registers, whose base address is starting from PCIe_Base_Address+0x0.

MSI registers in section 3.6 are Configuration Space Registers, whose base address is starting from PCIe_Base_Address+0x1000.

For example, in KeyStone devices, IRQ_EOI is 0x2180000+0x0+0x50=0x21800050, while MSI_CAP is 0x21800000+0x1000+0x50=0x21801050.

The purpose of MSI regsiters are used for the MSI interrupt generation mentioned in section 2.13, especially section 2.13.2.2 MSI Interrupt Generation in EP Mode.

Sincerely,

Steven

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0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Is it possible, for test purposes to generate an MSI interrupt by writting locally to the MSI_IRQ register?

I did notice that it seemed to set the appropriate bits in the IRQ_Status and IRQ_Status_Raw register. If you can generate interrupts this way, I apparently have not configured the intterupt correctly.

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

For KeyStone PCIe module, it is possible to generate interrupt by writing to the MSI_IRQ register, as mentioned in sections 2.13.3 and 2.13.4 in PCIe user's guide.

But generating MSI interrupt in this way is not compilable with the PCIe standard. It could be used for testing purpose and customized design among KeyStone devices. It does not guarantee the other external PCIe module will accept this. For the general purpose, you can refer the standard MSI generation method (EP triggers interrupt to RC) as mentioned in the PCIe user's guide as well (section 2.13.2.2).

Sincerely,

Steven

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0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Steven,

Yes we are going to implement a custom design with the DSP configured as an EP but also receiving msi interrupts.

Is it possible to generate an interrupt by writing the MSI_IRQ register from the DSP side (not the PCIe side memory access ) for debug purposes only?

0 Steven Ji over 13 years ago in reply to Mark Swick

TI__Genius 12065 points

Mark,

The user's guide states that MSI_IRQ is written by the "remote device". And my quick testing shows that the local DSP could NOT generate the interrupt by writing to this register. So you probably need to have two PCIe setup for the testing that modify this register via remote PCIe link access instead of local DSP access.

Sincerely,

Steven

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0 Mark Swick over 13 years ago in reply to Steven Ji

Intellectual 565 points

Thanks,

That is what I have been seeing.

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PCIe Documentation problem MSI registers