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C6678 - Interrupt behaviour clarification

Joseph Gagnon
Prodigy 200 points

Hello,

On the otherwise excellent interrupt clarification page (http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices#Using_CSL.C2.A0APIs) I found one disconcerting phrase: "Nesting mode is not supported in KeyStone devices"

I hope this means that nested interrupts have to be manually configured. I hope this does not mean that nested interrupts of any form are completely unavailable on the C6678.

Can you greatly expand upon the one line on that page, please? I have a system that I am porting to the C6678 that depends upon nesting interrupts. I am comfortable with manual register read/write operations but not having that functionality will be a major problem. Without nesting, multiple interrupt levels aren't especially useful: I could just have a main function and a single interrupt function that manually queue tasks in priority FIFOs and service the next highest task after I finish the previous one.

Thank you for your time

Joseph Gagnon

JDSU

Senior Software Systems Engineer

  • 0
    TI__Genius 12065 points

    Joseph,

    "Nesting mode is not supported" means the hardware assist of nesting feature is not supported. But the user could always use the purely software algorithm to implement the nesting in KeyStone devices. 

    If hardware nesting is supported, the hardware could perform the nesting (i.e. after an interrupt triggered at a priority, only interrupts above that priority are allowed) or the software could use some memory map registers (MMR) to set the priority to nest.

    Since the hardware support and nesting related MMRs are not available in KeyStone devices, the user could not rely on the hardware or a single write to MMR to implement the nesting.

    But there is always the most basic support available because each interrupt has an enable/disable MMR bit.  So a fully software nesting function is possible by making software know all the priorities and then write to the interrupt enable registers manually. And the best place to do this is in the initial ISR entry code so that the interrupts are disabled before the actual servicing begins.

    Hope it answers your question.

  • 0 in reply to Steven Ji
    Prodigy 200 points

    Hi Steven,

    Yes, this answers my question. Cheerfully enough, it answers it with the interpretation I was hoping was correct. As I had mentioned, I am comfortable with register r/w so this won't be a big problem.

    Happy Friday,

    Joseph Gagnon