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Memory Problem In C6678

Avinash Neethi1
Expert 2125 points
Other Parts Discussed in Thread: TMS320C6678

Hi,

     We were working in dual DSP(C6678) project. In that 1GB DDR3 is connected with each DSP. We have 5 micron chip(4 chip each of 256KB and 1 chip for ECC). I have configured the DDR3 of DSP1 to 64bit and I can able to access the memory perfectly of 64bit. But i configured the DDR3 of DSP2 to 64bit, But i cannot able to access the 64bit. I can able to access the first 3 DDR chip but i can't able to access the 4th DDR chip. The changes between the DSP1 and DSP2 gel is DATA_WRLVL_INIT_RATIO and DATA_GTLVL_INIT_RATIO all the other value remain the same. This problem remains the same for our second board also .I attached the DDR_Phy_cal of our board along with the Gel file. What can be the problem? How to rectify it? Can any one reply as soon it is very urgent.

Regards

Avinash Neethi

5516.DDR3_6678.rar

  • 0
    TI__Guru* 84110 points

    Avinash,

    Please clarify the following:

    1. What is the data width of each of the DDR3 Micron chips?
    2. Are the DDR3 layouts identical between the two DSPs? If not, what are the differences?
    3. When you say you cannot access the 4th DDR chip, exactly what do you mean? Do you read random values, occasional errors, all 0's, all 1's, or something else?
    4. Does the second board show the exact same access problems, with the 4th DDR chip only and with the same data signature?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2125 points

    Hi Randy P,

    1. What is the data width of each of the DDR3 Micron chips?

                    Each DDR3 Micron chips of 16bit (4chips * 16bit  =64bit).


    2. Are the DDR3 layouts identical between the two DSPs? If not, what are the differences?

    Yes DDR3 layouts identical between two DSP's.


    3.When you say you cannot access the 4th DDR chip, exactly what do you mean? Do you read random values, occasional errors, all 0's, all 1's, or something else?

                     In my first board one 16 bit is always 0's but for DSP1 and DDR3 is working perfectly. We have also checked the address and data lines.

    0x5A5A5A5A      0x00005A5A        0x5A5A5A5A             0x00005A5A        0x5A5A5A5A       0x00005A5A      
    0x5A5A5A5A      0x00005A5A        0x5A5A5A5A             0x00005A5A        0x5A5A5A5A       0x00005A5A
    0x5A5A5A5A      0x00005A5A

                   The changes in the DSP1 gel file and DSP2 gel file is DATA_WRLVL_INIT_RATIO  and DATA_GTLVL_INIT_RATIO and all the other values are same .  

    4. Does the second board show the exact same access problems, with the 4th DDR chip only and with the same data signature?

    A.       In my second board I can't run the gel file . It show's the bellow error

              Global_Default_Setup() cannot be evaluated.
              Evaluation canceled

    B.       Second Error Shown is  

               C66xx_8: GEL Output: DDR done

               C66xx_8: GEL Output: DDR3 memory test... Started
               C66xx_8: GEL Output: DDR3 memory test... Failed

    5.  will the DATA_WRLVL_INIT_RATIO  and DATA_GTLVL_INIT_RATIO cause any problem for memory accessing?

         Regards,

    Avinash Neethi      

  • 0 in reply to Avinash Neethi1
    TI__Guru* 84110 points

    Avinash,

    By marking these posts Verified Answer, people looking for threads to help with will not be looking at your thread to try to provide additional help. Please use that mark only when you are satisfied with the answer to your question. For these two threads that you have marked, if you are still looking for help, please remove those Answered marks.

    Why do you have different values for DATA_WRLVL_INIT_RATIO and DATA_GTLVL_INIT_RATIO? With identical layouts, the timing should also be identical for these values. How different are these values?

    You will want to look at the signals at the failing 4th DDR device and compare those to the signals on the other DDR devices on that same device, for convenience.

    You will want to look deeper into the Global_Default_Setup() function to determine where it is failing. This will help provide a hint about where the failure is.

    Look at power supplies and clocks to make sure they are noise-free and look correct.

    Compare the schematics and layouts between DSP1 and DSP2 to find what errors may have occured in the board design.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Mastermind 30825 points

    I went ahead and rejected the answers (removed the 'Verified Answer' markings) since they were only investigative and not solutions as RandyP has indicated.

    Best Regards,

    Chad

  • 0 in reply to RandyP
    Expert 2125 points

    Hi Randy,

    Why do you have different values for DATA_WRLVL_INIT_RATIO and DATA_GTLVL_INIT_RATIO? With identical layouts, the timing should also be identical for these values. How different are these values?

    DSP1-DDR3 values are 

    DATA0_WRLVL_INIT_RATIO = 0x63;
    DATA1_WRLVL_INIT_RATIO = 0x63;
    DATA2_WRLVL_INIT_RATIO = 0x63;
    DATA3_WRLVL_INIT_RATIO = 0x63;
    DATA4_WRLVL_INIT_RATIO = 0x63;
    DATA5_WRLVL_INIT_RATIO = 0x63;
    DATA6_WRLVL_INIT_RATIO = 0x63;
    DATA7_WRLVL_INIT_RATIO = 0x63;
    DATA8_WRLVL_INIT_RATIO = 0x63;

    DATA0_GTLVL_INIT_RATIO = 0xEB;
    DATA1_GTLVL_INIT_RATIO = 0xEB;
    DATA2_GTLVL_INIT_RATIO = 0xEB;
    DATA3_GTLVL_INIT_RATIO = 0xEB;
    DATA4_GTLVL_INIT_RATIO = 0xEC;
    DATA5_GTLVL_INIT_RATIO = 0xEC;
    DATA6_GTLVL_INIT_RATIO = 0xEC;
    DATA7_GTLVL_INIT_RATIO = 0xEC;
    DATA8_GTLVL_INIT_RATIO = 0xEB;

    DSP2-DDR3

    DATA0_WRLVL_INIT_RATIO = 0x9D;
    DATA1_WRLVL_INIT_RATIO = 0x9D;
    DATA2_WRLVL_INIT_RATIO = 0x9D;
    DATA3_WRLVL_INIT_RATIO = 0x9D;
    DATA4_WRLVL_INIT_RATIO = 0x9D;
    DATA5_WRLVL_INIT_RATIO = 0x9D;
    DATA6_WRLVL_INIT_RATIO = 0x9D;
    DATA7_WRLVL_INIT_RATIO = 0x9D;
    DATA8_WRLVL_INIT_RATIO = 0x9D;

    DATA0_GTLVL_INIT_RATIO = 0xFC;
    DATA1_GTLVL_INIT_RATIO = 0xFC;
    DATA2_GTLVL_INIT_RATIO = 0xFC;
    DATA3_GTLVL_INIT_RATIO = 0xFC;
    DATA4_GTLVL_INIT_RATIO = 0xFC;
    DATA5_GTLVL_INIT_RATIO = 0xFC;
    DATA6_GTLVL_INIT_RATIO = 0xFC;
    DATA7_GTLVL_INIT_RATIO = 0xFC;
    DATA8_GTLVL_INIT_RATIO = 0xFC.

    We have also probe the address line and data lines. They were in the same state for both the 4th DDR chip and the 3rd DDR chip. We have also checked the power supplies and the clock they were in the correct form. And I have compared the DSP1 and DSP2 schematic and layout , both are same.

    Is there any other way to check that the DDR3 register values are correct?

    Regards,

    Avinash N 


  • 0 in reply to RandyP
    Expert 2125 points

    Hi Randy,

    Why do you have different values for DATA_WRLVL_INIT_RATIO and DATA_GTLVL_INIT_RATIO? With identical layouts, the timing should also be identical for these values. How different are these values?

    DSP1-DDR3 values are 

    DATA0_WRLVL_INIT_RATIO = 0x63;
    DATA1_WRLVL_INIT_RATIO = 0x63;
    DATA2_WRLVL_INIT_RATIO = 0x63;
    DATA3_WRLVL_INIT_RATIO = 0x63;
    DATA4_WRLVL_INIT_RATIO = 0x63;
    DATA5_WRLVL_INIT_RATIO = 0x63;
    DATA6_WRLVL_INIT_RATIO = 0x63;
    DATA7_WRLVL_INIT_RATIO = 0x63;
    DATA8_WRLVL_INIT_RATIO = 0x63;

    DATA0_GTLVL_INIT_RATIO = 0xEB;
    DATA1_GTLVL_INIT_RATIO = 0xEB;
    DATA2_GTLVL_INIT_RATIO = 0xEB;
    DATA3_GTLVL_INIT_RATIO = 0xEB;
    DATA4_GTLVL_INIT_RATIO = 0xEC;
    DATA5_GTLVL_INIT_RATIO = 0xEC;
    DATA6_GTLVL_INIT_RATIO = 0xEC;
    DATA7_GTLVL_INIT_RATIO = 0xEC;
    DATA8_GTLVL_INIT_RATIO = 0xEB;

    DSP2-DDR3

    DATA0_WRLVL_INIT_RATIO = 0x9D;
    DATA1_WRLVL_INIT_RATIO = 0x9D;
    DATA2_WRLVL_INIT_RATIO = 0x9D;
    DATA3_WRLVL_INIT_RATIO = 0x9D;
    DATA4_WRLVL_INIT_RATIO = 0x9D;
    DATA5_WRLVL_INIT_RATIO = 0x9D;
    DATA6_WRLVL_INIT_RATIO = 0x9D;
    DATA7_WRLVL_INIT_RATIO = 0x9D;
    DATA8_WRLVL_INIT_RATIO = 0x9D;

    DATA0_GTLVL_INIT_RATIO = 0xFC;
    DATA1_GTLVL_INIT_RATIO = 0xFC;
    DATA2_GTLVL_INIT_RATIO = 0xFC;
    DATA3_GTLVL_INIT_RATIO = 0xFC;
    DATA4_GTLVL_INIT_RATIO = 0xFC;
    DATA5_GTLVL_INIT_RATIO = 0xFC;
    DATA6_GTLVL_INIT_RATIO = 0xFC;
    DATA7_GTLVL_INIT_RATIO = 0xFC;
    DATA8_GTLVL_INIT_RATIO = 0xFC.

    We have also probe the address line and data lines. They were in the same state for both the 4th DDR chip and the 3rd DDR chip. We have also checked the power supplies and the clock they were in the correct form. And I have compared the DSP1 and DSP2 schematic and layout , both are same.

    Is there any other way to check that the DDR3 register values are correct?

    Regards,

    Avinash N 

  • 0 in reply to Avinash Neethi1
    TI__Guru* 84110 points

    Avinash,

    "Why" do you have different value? Where did you get these values from?

    Also, I do not understand how the data lines can be in the same state for the 4th DDR chip and the 3rd DDR chip since the 4th DDR chip only returns 0x0000.

    You will want to look at the data lines during a continuous write test and then during a continuous read test. This will help you to see if the correct data is being written to the DDR3 bus and whether any data is being returned from the 4th DDR device like it is from the 3rd DDR device.

    Try using the exact same values for your Write Level and Gate Level initial values. Try the first set on both DSPs, then try the second set on both DSPs.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2125 points

    Hi Randy,

    We were currently working on the second board. In the second board we use one rev-1.0 and one rev-2.0(TMS320c6678 REV-1.0,REV-2.0).

    I am porting the first board GEL file for the second board. In our first board both the DSP are REV-1.0, But in our second board one is REV-1.0 and one is REV-2.0.

    When i Execute the GEL file through CCS, The error is shown in the MAIN PLL configuration section itself.

    QUIRES:

    1. What is the difference between TMS320C6678 REV-1.0 And REV-2.0 Chip?

    2. What changes should be done in the GEL file for REV-2.0?

    3. Sample GEL File for TMS320C6678 REV-2.0 can you provide?

    Regards,

    Avinash N

  • 0 in reply to Avinash Neethi1
    TI__Guru* 84110 points

    Avinash,

    The difference between rev 1.0 and rev 2.0 of the TMS320C6678 silicon are detailed in the errata document which is available from the TMS320C6678 Product Folder. Table 3 lists the Advisories and Usage Notes with notation of which ones apply to the two silicon revisions. Mostly, rev 2.0 implements fixes for items that were found in rev 1.0, but there are some items that were not issues for rev 1.0 but are listed for rev 2.0.

    GEL files are provided with the MCSDK (omp folder tree) and with the emulation pack updates (emupack) with CCSv5 updates ( ccsv5\ccs_base\emulation\boards\evmc6678l\gel ).

    Regards,
    RandyP

  • 0 in reply to RandyP
    Expert 2125 points

    Hi RandyP,

    can you provide some ideas for the issue we are facing in DDR3 Accessing.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/382674/1348674.aspx#1348674

    Can anyone response as soon as possible. 

    Regards,

    Avinash N