DDR3 settings on C6678

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Other Parts Discussed in Thread: TMS320C6678

We are wondering if we need to run a shmoo test to find the optimal settings for the DDR3 attached to the DSP on our platform. The DDR3 settings are currently similar to the C6678 EVM – the small differences as marked below. Would you be able to help us on this or help direct the question?

ddr3_setup_auto_lvl_1333()

{

int i,TEMP,startlo, stoplo,starthi, stophi;

KICK0 = KICK0_UNLOCK;

KICK1 = KICK1_UNLOCK;

/***************** 2.2 DDR3 PLL Configuration ************/

DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1 50-70ms

DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1 50-70ms

DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ ~60ms

//Wait for 5us min. Actual delay in GEL here is in tens of ms

DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit

//Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us. Actualy delay between 2 GEL steps = ~6ms

/**************** 3.0 Leveling Register Configuration ********************/

/* Using partial automatic leveling due to errata */

/**************** 3.2 Invert Clock Out ********************/

DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field

DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100

DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1

DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15

DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS

//Values with invertclkout = 1

/**************** 3.3+3.4 Partial Automatic Leveling ********************/

DATA0_WRLVL_INIT_RATIO = 0x5E;

DATA1_WRLVL_INIT_RATIO = 0x5E;

DATA2_WRLVL_INIT_RATIO = 0x5E;

DATA3_WRLVL_INIT_RATIO = 0x51;

DATA4_WRLVL_INIT_RATIO = 0x38;

DATA5_WRLVL_INIT_RATIO = 0x3A;

DATA6_WRLVL_INIT_RATIO = 0x24;

DATA7_WRLVL_INIT_RATIO = 0x20;

DATA8_WRLVL_INIT_RATIO = 0x44;

DATA0_GTLVL_INIT_RATIO = 0xDD;

DATA1_GTLVL_INIT_RATIO = 0xDD;

DATA2_GTLVL_INIT_RATIO = 0xBE;

DATA3_GTLVL_INIT_RATIO = 0xCA;

DATA4_GTLVL_INIT_RATIO = 0xA9;

DATA5_GTLVL_INIT_RATIO = 0xA7;

DATA6_GTLVL_INIT_RATIO = 0x9E;

DATA7_GTLVL_INIT_RATIO = 0xA1;

DATA8_GTLVL_INIT_RATIO = 0xBA;

//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0

DDR_DDRPHYC &= ~(0x00008000);

DDR_DDRPHYC |= (0x00008000);

DDR_DDRPHYC &= ~(0x00008000);

/***************** 2.3 Basic Controller and DRAM configuration ************/

DDR_SDRFC = 0x00005162; // enable configuration

DDR_SDTIM1 = 0x1113783C; // Same for Cultus Board RAC2

DDR_SDTIM2 = 0x60707FE3; // RAC2 Cultus. For EVM - 0x304F7FE3;

DDR_SDTIM3 = 0x559F86AF; // RAC2 Cultus. For EVM - 0x559F849F;

DDR_DDRPHYC = 0x0010010F;

DDR_ZQCFG = 0x70073214;

DDR_PMCTL = 0x0;

/* DDR_SDCFG = 0x63062A32; */

//New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;

// last config write DRAM init occurs

DDR_SDCFG = 0x63062AB2; // Cultus Board RAC2

DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz]

RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead

//Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.

//Actual time = ~10-15 ms

GEL_TextOut("\nDDR3 initialization is complete.\n");

}

Thanks

-Anand

over 12 years ago

0 Chad Courtney over 12 years ago

TI__Mastermind 30825 points

EDIT: Merged Threads

Mike,

There are Application Notes on the TMS320C6678 <-- Product Page that cover this. Specifically the DDR3 HW Design Guidelines for Keystone Devices and the Keystone DDR3 Initialization Guidelines. No Schmoo's required.

Best Regards,

Chad

0 Michael Questo over 12 years ago

TI__Expert 6000 points

Hello C6678 Champs,

I have a customer have is trying to optimize their DDR3 timings. Their settings are currently similar to the C6678 EVM, except for the small differences highlighted below.

They're wondering if they need to run a shmoo test (http://en.wikipedia.org/wiki/Shmoo_plot) to find the optimal DDR3 settings for their custom boards. I've linked the DDR3 Memory Controller Guide from the product landing page for reference.

C6678 Product Page: http://www.ti.com/product/tms320c6678

KeyStone Architecture DDR3 Memory Controller: http://www.ti.com/lit/ug/sprugv8c/sprugv8c.pdf

The Code:

ddr3_setup_auto_lvl_1333()

{

int i,TEMP,startlo, stoplo,starthi, stophi;

KICK0 = KICK0_UNLOCK;

KICK1 = KICK1_UNLOCK;

/***************** 2.2 DDR3 PLL Configuration ************/

DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1 50-70ms

DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1 50-70ms

DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ ~60ms

//Wait for 5us min. Actual delay in GEL here is in tens of ms

DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit

//Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us. Actualy delay between 2 GEL steps = ~6ms

/**************** 3.0 Leveling Register Configuration ********************/

/* Using partial automatic leveling due to errata */

/**************** 3.2 Invert Clock Out ********************/

DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field

DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100

DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1

DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15

DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS

//Values with invertclkout = 1

/**************** 3.3+3.4 Partial Automatic Leveling ********************/

DATA0_WRLVL_INIT_RATIO = 0x5E;

DATA1_WRLVL_INIT_RATIO = 0x5E;

DATA2_WRLVL_INIT_RATIO = 0x5E;

DATA3_WRLVL_INIT_RATIO = 0x51;

DATA4_WRLVL_INIT_RATIO = 0x38;

DATA5_WRLVL_INIT_RATIO = 0x3A;

DATA6_WRLVL_INIT_RATIO = 0x24;

DATA7_WRLVL_INIT_RATIO = 0x20;

DATA8_WRLVL_INIT_RATIO = 0x44;

DATA0_GTLVL_INIT_RATIO = 0xDD;

DATA1_GTLVL_INIT_RATIO = 0xDD;

DATA2_GTLVL_INIT_RATIO = 0xBE;

DATA3_GTLVL_INIT_RATIO = 0xCA;

DATA4_GTLVL_INIT_RATIO = 0xA9;

DATA5_GTLVL_INIT_RATIO = 0xA7;

DATA6_GTLVL_INIT_RATIO = 0x9E;

DATA7_GTLVL_INIT_RATIO = 0xA1;

DATA8_GTLVL_INIT_RATIO = 0xBA;

//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0

DDR_DDRPHYC &= ~(0x00008000);

DDR_DDRPHYC |= (0x00008000);

DDR_DDRPHYC &= ~(0x00008000);

/***************** 2.3 Basic Controller and DRAM configuration ************/

DDR_SDRFC = 0x00005162; // enable configuration

DDR_SDTIM1 = 0x1113783C; // Same for Cultus Board RAC2

DDR_SDTIM2 = 0x60707FE3; // RAC2 Cultus. For EVM - 0x304F7FE3;

DDR_SDTIM3 = 0x559F86AF; // RAC2 Cultus. For EVM - 0x559F849F;

DDR_DDRPHYC = 0x0010010F;

DDR_ZQCFG = 0x70073214;

DDR_PMCTL = 0x0;

/* DDR_SDCFG = 0x63062A32; */

//New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;

// last config write DRAM init occurs

DDR_SDCFG = 0x63062AB2; // Cultus Board RAC2

DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz]

RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead

//Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.

//Actual time = ~10-15 ms

GEL_TextOut("\nDDR3 initialization is complete.\n");

}

0 Tom Johnson 16214 over 12 years ago in reply to Michael Questo

TI__Mastermind 46460 points

Michael,

No, you do not need to do a schmoo to develop the initial settings for the DDR3 interface on the C6678. This is a deterministic process. First, you need to lay out the board by following the routing rules stated in the DDR3 Design Requirements for KeyStone Devices at: http://www.ti.com/litv/pdf/sprabi1a. Most importantly, the length matching rules for the net classes need to be met. I recommend creation of a spreadsheet to validate these rules are met. An example spreadsheet generated from the layout tool is attached here.

8473.Shn_EVM_DDR3_Rules_1201.xls

From this table, you can extract the routed lengths for each of the data groups and for the address/command/control/clock fly-by routes from the controller to each of the DRAMs. This information must be placed into the PHY_CALC spreadsheet. It and its associated Ap Note are available at: http://www.ti.com/litv/pdf/sprabl2a and http://www.ti.com/litv/zip/sprabl2a. The PHY_CALC spreadsheet will provide the initialization values needed for your board design. These links will also provide the REG_CALC spreadsheet which can be used to calculate the remainder of the necessary configuration values.

If you have done all of this and your design is not functional, please provide the routed length spreadsheet, PHY_CALC and REG_CALC spreadsheets for review.

Also, please describe your mode of failure and you method for testing the robustness of the memory interface?

Tom

0 Matt Pattison1 over 12 years ago in reply to Tom Johnson 16214

Prodigy 20 points

Hi Tom,

My name is Matt Pattison, I was the HW engineer that did the board design. I used the TI DDR doc to come up with the layout constraints. The enforcement of the constraints in the layout was done via functionality built into the layout tool not by a spreadsheet. So it looks like I will need to extract the flyby lengths to input into the PHY_CALC spreadsheet. I will work on this (along with the REG_CALC spreadsheet) and provide the new register values to our SW engineers to try out.

Am I correct in understanding that these register values will just provide a "good" starting point for the DDR3 timing and that the auto-leveling will then fine tune it based on current temp/voltage/process variations? And therefore a schmoo type test isn't needed to find the optimal settings.

-Matt

0 Matt Pattison1 over 12 years ago in reply to Matt Pattison1

Prodigy 20 points

Hi Tom,

I was reviewing the default values in the "DDR3 Register Calc v4" spreadsheet. We use the same samsung part (K4B2G1646C 1333) that the spreadsheet had selected when I first opened it. Actually we use the 1600 speed grade version but are running it at 1333, so I'm assuming the same timings will apply. I reviewed all the timings against the datasheet and everything made sense. The only part that did not was the SDRAM configuration section. First, why is DYN_ODT set to "off"? Is this typical for using a single rank of x16 parts soldered down on the board? We only have pasive terminations on addr/cmd/clk signals.

Second question is on the ROWSIZE setting. The samsung datasheet says the row address is A0-A13, wouldn't this be 14 row bits not 13? The spreadsheet had this set to 13.

-Matt

0 Tom Johnson 16214 over 12 years ago in reply to Matt Pattison1

TI__Mastermind 46460 points

Matt,

The DDR3 controller drives the ODT signal active when it expects the SDRAM to assert the on die termination. It does this during every write cycle as needed for proper data-group signal termination. There is no need for an additional termination that is based on the operating mode of the SDRAM. Note that ODT operates only on the data-group signals. It does not operate on any of the "fly-by" signals (ADDRES, COMMAND, CONTROL and CLOCK). The fly-by signals must all be routed in a bussed configuration with VTT terminations at the end - no branches and only closely managed, short stubs at each SDRAM.

The ROWSIZE setting should be corrected for completeness. This setting is actually not required any longer. If you refer to the logical mapping of DSP address pins to the SDRAM pins in Section 2.5 of the KeyStone Architecture DDR3 Memory Controller User Guide (SPRUGV8), you will see that the size of the row bits does not change the bit mapping - they are the most significant ones. The other fields (PAGESIZE, EBANK and IBANK) must be correctly set to access the entire SDRAM memory array. If you access larger addresses that the physical memory supports, the memory wraps (it is aliased).

Tom

0 Tom Johnson 16214 over 12 years ago in reply to Matt Pattison1

TI__Mastermind 46460 points

Matt,

The PHY_CALC spreadsheet does provide a robust starting point so that the DDR3 PHY converges to the optimum point. This is a deterministic process so no schmoo is needed. Proper use of the PHY_CALC spreadsheet is required. There is only a limited range of values that are guaranteed to converge correctly. This range of initial values change from board to board.

Tom

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DDR3 settings on C6678