Hyperlink problem on 66AK2H12

To test Shannon Hyperlink,

• you need to put the DSP in no-boot mode (not Hyperlink boot mode),
• use the 6678 GEL file under C:\ti\ccsv5\ccs_base\emulation\boards\evmc6678l\gel\evmc6678l.gel to initialize the DSP (not xtcievmk2x.gel).
• example is C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\hyplnk_exampleProject (not MCSDK  3.0.1.12)
• Inside the example project, you need to edit hyplnkLLDCfg.h file to select your reference clock (312.50 MHz), num of lane, serial rate and loopback or not and rebuild the test application
• It is good to make sure that loopback is working before moving to EVM to EVM test

 To test Hawking Hyperlink,

• you need to put the EVM in no-boot mode
• Use xtcievmk2x.gel to initialize the DSP
• Use the example under C:\ti\pdk_keystone2_1_00_00_11\packages\exampleProjects\hyplnk_K2HC66BiosExampleProject
• Again you need to edit the same hyplnkLLDCfg.h file for configuration and rebuild the test
• It is good to make sure that loopback is working before moving to EVM to EVM test

I don't know how you connect K2HEVM to 6678 EVM. It should be K2HEVM -----Keystone 2 RTM BOC-----Hyperlink cable ----- 6678 EVM.

Let's make sure loopback mode work for both cards before moving to card to card.

Regards, Eric 

And, 312.50 MHz reference clock, 4 lanes, 6.25Gb rate should work in loopback mode.

Regards, Eric

Hello Eric,

I’m using XTCIEVMK2X evaluation kit as a reference. As you suggested, I’m first trying to get the loopback mode working. However, it keeps failing.

First I defied those settings in the configuration file:

Later, after your suggestion I set it to:

But the application behavior is exactly the same regardless the selected settings.

When I try to use loopback mode without any modifications, then the application cannot pass “SB PLL Status Poll” (line #483 in hyplnkLLDIFace.c file). Here is the output:

After modifying CSL_HyperlinkSerdesGetStatus function to always return “OK” values (I do not expect SerDes PLL to be locked while doing internal loopback, is this the right assumption?), the example crashes when accessing remote device’s registers. The application output:

Can you please tell me, how can I proceed to solve this problem?

Hello Eric,

With the tips you send me I was finally able to successfully run the loopback example on 66AK2H12 on evaluation kit and also on my proto board. That’s already a step forward.

However, I still would like to verify if the 66AK2H12 can communicate with TMS320C6678 over Hyperlink in my proto device. Because I only have a single debugger, I thought I can set TMS320C6678 in Hyperlink bootmode and run the Hyperlink example on 66AK2H12. If 66AK2H12 can read the memory of its link partner, I can say that my link is working.

Can you please tell me if this is a good assumption? Is the Hyperlink example able to communicate with a remote device set to Hyperlink bootmode?

If you set 6678 in Hyperlink bootmode, the configuration is set by pin switch for reference clock and data rate. The K2H side software you need to match your 6678 setting. This should work.

How do you physically connect them together? Do you have KS2 RTM BOC and Hyperlink cable?

Regards, Eric

lding said:

How do you physically connect them together? Do you have KS2 RTM BOC and Hyperlink cable?

I don’t use any cable, the devices are fixed connected on the PCB.

Hello,

I'm working on the same project. Loopback mode on the Hawking works, but when we change the settings to use hyperlink, the program crashes when accessing remote registers (just like the loopback example did):

[C66xx_0] Version #: 0x02000007; string HYPLNK LLD Revision: 02.00.00.07:Jul 30 2013:10:02:29

About to do system setup (PLL, PSC, and DDR)

Power domain is already enabled.  You probably re-ran without device reset (which is OK)

Constructed SERDES configs: PLL=0x00000250; RX=0x0046c485; TX=0x000cc305

system setup worked

About to set up HyperLink Peripheral

============================Hyperlink Testing Port 0

========================================== begin registers before initialization ===========

Revision register contents:

  Raw    = 0x4e902101

  Scheme = 1

  BU     = 0

  Func   = 0x0e90

  RTL    = 4

  cust   = 0

  revMaj = 1

  revMin = 1

Status register contents:

  Raw        = 0x00003004

  swidthin   = 0

  swidthout  = 0

  serialHalt = 1

  pllUnlock  = 1

  rPend      = 0

  iFlow      = 0

  oFlow      = 0

  rError     = 0

  lError     = 0

  nfEmpty3   = 0

  nfEmpty2   = 0

  nfEmpty1   = 0

  nfEmpty0   = 0

  sPend      = 1

  mPend      = 0

  link       = 0

Link status register contents:

  Raw       = 0x00000000

  txPlsReq  = 0

  txPlsAck  = 0

  txPmReq   = 0

  txRSync   = 0

  txPlsOK   = 0

  txPhyEn   = 0

  txFlowSts = 0

  rxPlsReq  = 0

  rxPlsAck  = 0

  rxPmReq   = 0

  rxLSync   = 0

  rxPhyEn   = 0

  rxPhyPol  = 0

Control register contents:

  Raw             = 0x00000000

  intLocal        = 0

  statusIntEnable = 0

  statusIntVec    = 0

  int2cfg         = 0

  serialStop      = 0

  iLoop           = 0

  reset           = 0

Control register contents:

  Raw        = 0x00000000

  sglErrCor  = 0

  dblErrDet  = 0

============== end registers before initialization ===========

============== begin registers after initialization ===========

Status register contents:

  Raw        = 0x04400005

  swidthin   = 4

  swidthout  = 4

  serialHalt = 0

  pllUnlock  = 0

  rPend      = 0

  iFlow      = 0

  oFlow      = 0

  rError     = 0

  lError     = 0

  nfEmpty3   = 0

  nfEmpty2   = 0

  nfEmpty1   = 0

  nfEmpty0   = 0

  sPend      = 1

  mPend      = 0

  link       = 1

Link status register contents:

  Raw       = 0xccf00cff

  txPlsReq  = 3

  txPlsAck  = 0

  txPmReq   = 3

  txRSync   = 0

  txPlsOK   = 0

  txPhyEn   = 15

  txFlowSts = 0

  rxPlsReq  = 0

  rxPlsAck  = 0

  rxPmReq   = 3

  rxLSync   = 0

  rxPhyEn   = 15

  rxPhyPol  = 15

Control register contents:

  Raw             = 0x00006202

  intLocal        = 1

  statusIntEnable = 1

  statusIntVec    = 2

  int2cfg         = 0

  serialStop      = 0

  iLoop           = 1

  reset           = 0

============== end registers after initialization ===========

Waiting 5 seconds to check link stability

Precursors 0

Postcursors: 19

Link seems stable

About to try to read remote registers

Both the Hawking and the Shannon are set to 156.25MHz ref clock and 6.25G data rate. The Shannon is set to Hyperlink bootmode and the example program is run on the Hawking. Could it be that we are overlooking something?

Regards,

Arno

Arno,

If you are doing 6678 to K2H test, why the "iLoop           = 1" ? Did you comment out the #define Hylnk_loopback and rebulit the code on K2H side?

Regards, Eric

Hello Eric,

I've made sure that that define was commented out, rebuilt the code and ran the program again. The only change in output is the iLoop variable that is now 0,  but the device still hangs while trying to read the remote registers.

Regards, Arno

So, you saw: 

Link seems stable

About to try to read remote registers

in the CIO console when K2H in non-loopback mode.

What is the possibility to connect the 6678 with the debugger and try the no-boot mode and load the DSP program? Then move the debugger to K2H load program and run?

Regards, Eric

Hello,

Sorry for the late response. I have been working to get Hawking connection to Shannon via Hyperlink.

Below is working setup used in our verification (I realized you have the KS2 and KS1 connected via wire in your prototype card, you have two machines with seperate XDS560 PCI cards. Therefore you also have two debug environments).

• HW: Hawking PG 1.0 EVM ---- KS2 RTM BOC Rev 1.0 (Hyperlink Port 0)------ Molex cable ------ 6678 Rev 3B EVM
• Software:

            -Hawking based on MCSDK 3.0.2 pre-release, configured for Hyperlink port 0, 312.5MHz clock, 3.125 Gb/s baud rate and x4 lanes

            -Shannon based on MCSDK 2.1.2.6, 312.5 MHz clock (can’t be changed on EVM), 3.125 Gb/s baud rate and x4 lanes

            -Both EVM are set to no-boot mode, CCS is used to load code to core 0 of each EVM, GEL file runs first before loading the code.  

Some notes:

• 6.25 Gb/s doesn’t work on my setup, this is related to my EVM connection via a longer cable. 3.125Gb/s worked.
• It is advised to drive both Hyperlink ends with a common reference clock, on EVM we have to use asynchronous clocks though, generated by the crystal on each EVM.
• The 3.0.2 has many serdes functions regrouped/changed and is not GA yet.
• The 3.0.1 GA release doesn’t have the serdes configuration for 312.5M refer clock

For your verification, 

• I uploaded the pre-build out files.
• Since Hawking side is built with reference clock 312.5Mhz, you don't need to change EVM clock via BMC console 

In seperate e-mails, you had some question about CSL serdes functions like CSL_HYPERLINK_156p25Mhz_6p25g_SerDes_Init(), where those registers are documented? I believe the purpose is to change lane rate to a lower value. In the 3.0.2 GA release, those functions will be re-grouped into other CSL functions and the those registers should not be touched/concerned. Changing lane rate is done in application code via lane_rate in packages\ti\drv\hyplnk\example\common\hyplnkLLDIFace.c:

defined hyplnk_EXAMPLE_SERRATE_06p250

linkRate = CSL_SERDES_LINK_RATE_6p25G;

lane_rate = CSL_SERDES_LANE_FULL_RATE; ======> this is 6.25 Gb/s

CSL_SERDES_LANE_HALF_RATE
CSL_SERDES_LANE_QUARTER_RATE

Please let me know if you can verify this and eastablish a working case. Then, we will see how to get you the source code, or want lower baud rate or want Hyperlink boot mode     

Regards, Eric

Uploaded my pre-builts:

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/6082.hyplnk_5F00_exampleProject_5F00_312.5_5F00_3.125_5F00_4x.out

hyplnk_exampleProject_312.5_3.125_4x.out is for Shannon side.

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/1832.hyplnk_5F00_K2HC66BiosExampleProject_5F00_312.5_5F00_3.125_5F00_x4_5F00_port0.out

hyplnk_K2HC66BiosExampleProject_312.5_3.125_x4_port0.out is for Hawking side.

Regards, Eric 

Hello Eric,

Thank you for your support, I will try it out. But one big remark, our reference clock is 156.25MHz so I think this will be problematic. 
We use for both sides a 156.25MHz reference clock.  So is it possible that you generate an output file with a reference clock configured at 156.25MHz. I think starting with 3.125 Gbaud is good approach. So if possible with the internal workings of the DSP I suggess to stay at this baudrate. 

Thanks!

Hello Eric,

I have loaded the programs via 'load program' in the run menu:

I got the same behaviour (but I was not expecting that it is going to work because of the wrong reference clock setting): 

"

[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03c78d19; lock = 1
SERDES_STS (32 bits) contents: 0x01020409; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 1 Analysis: 0,1,0,1,0,1,0,1
Postcursors: 19 Analysis: 0,1,0,1,0,1,0,1
Link seems stable
About to try to read remote registers

"
After this, the debugger hangs. 

-Maybe can you provide me also the source code of the projects?
-Is it possible that it prints more diagnostic information?
-I have an idea that an internal bus structure is stalled on something (sideband bus?) while waiting for a response.  

Hi,

Sorry I didn't realized that your clock is 156.25. Attached is the pre-builts for 156.25. Please note, this can't be verified on my setup due to 6678 EVM only works with 312.5 clock. Can you have a quick try?

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/3554.hyplnk_5F00_exampleProject_5F00_15625_5F00_3.125_5F00_4x.out

http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/7827.hyplnk_5F00_K2HC66BiosExampleProject_5F00_156.25_5F00_3.125_5F00_x4_5F00_port0.out

Regards, Eric

For the source code:

6678 side is based on MCSDK 2.1.2.6, the configuration is straightforward:

//#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG

#define hyplnk_EXAMPLE_REFCLK_156p25

//#define hyplnk_EXAMPLE_REFCLK_250p00

//#define hyplnk_EXAMPLE_REFCLK_312p50

/*****************************************************************************

* Select internal loopback or use the SERDES connection

*****************************************************************************/

//#define hyplnk_EXAMPLE_LOOPBACK

/*****************************************************************************

* Select number of lanes allowed

*****************************************************************************/

//#define hyplnk_EXAMPLE_ALLOW_0_LANES

//#define hyplnk_EXAMPLE_ALLOW_1_LANE

#define hyplnk_EXAMPLE_ALLOW_4_LANES

/*****************************************************************************

* Select a serial rate

*****************************************************************************/

//#define hyplnk_EXAMPLE_SERRATE_01p250

#define hyplnk_EXAMPLE_SERRATE_03p125

//#define hyplnk_EXAMPLE_SERRATE_06p250

//#define hyplnk_EXAMPLE_SERRATE_07p500

//#define hyplnk_EXAMPLE_SERRATE_10p000

//#define hyplnk_EXAMPLE_SERRATE_12p500

You can build by yourself.

For the Hawking side, the MCSDK 3.0.2 package is more than 1 GB. I am extracting the Hyperlink and CSL portion for you.

Regards, Eric

Here is the Hawking side code from MCSDK 3.0.2 pre-build, please note this is an engineering release and not fully tested, it is only for your reference. The 3.0.2 GA is expected on Oct 2, please upgrade to GA release later on.

For now, you can patch your MCSDK 3.0.0 or 3.0.1 release based on my attachments below.

The hyplnk.rar is to replace your C:\ti\pdk_keystone2_3_00_02_14\packages\ti\drv\hyplnk

The csl.rar is to replace your C:\ti\pdk_keystone2_3_00_02_14\packages\ti\csl

Can you build the same Hyperlink project?

If yes, the configuration is:

//#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG

#define hyplnk_EXAMPLE_REFCLK_156p25

//#define hyplnk_EXAMPLE_REFCLK_250p00

//#define hyplnk_EXAMPLE_REFCLK_312p50

/*****************************************************************************

* Select internal loopback or use the SERDES connection

*****************************************************************************/

//#define hyplnk_EXAMPLE_LOOPBACK

/*****************************************************************************

* Select number of lanes allowed

*****************************************************************************/

//#define hyplnk_EXAMPLE_ALLOW_0_LANES

//#define hyplnk_EXAMPLE_ALLOW_1_LANE

#define hyplnk_EXAMPLE_ALLOW_4_LANES

/*****************************************************************************

* Select a serial rate

*****************************************************************************/

//#define hyplnk_EXAMPLE_SERRATE_01p250

//#define hyplnk_EXAMPLE_SERRATE_03p125

#define hyplnk_EXAMPLE_SERRATE_06p250 =====> don't change this even for 3.125 G

//#define hyplnk_EXAMPLE_SERRATE_07p500

//#define hyplnk_EXAMPLE_SERRATE_10p000

//#define hyplnk_EXAMPLE_SERRATE_12p500

The different lane_rate is set in hyplnkLLDIFace.c:

#elif (hyplnk_EXAMPLE_HYPLNK_REF_KHZ == 156250)   
    refClock = CSL_SERDES_REF_CLOCK_156p25M;

#ifdef hyplnk_EXAMPLE_SERRATE_06p250
    linkRate = CSL_SERDES_LINK_RATE_6p25G;
    lane_rate = CSL_SERDES_LANE_FULL_RATE;
#else
    #error Unsupported Link Rate 
#endif /* Link Rate */

CSL_SERDES_LANE_FULL_RATE is 6.25

CSL_SERDES_LANE_HALF_RATE is 3.125

CSL_SERDES_LANE_QUARTER_RATE is 1.5625

Regards, Eric

0336.hyplnk.rar

2161.csl.rar

Hello Eric,

Great news, the test passes. In the meantime I also was working at the code and I checked the gel file of the 66AK2H12. 
Further I checked again the settings of the C6678. The following setting was crucial to get the test working:

"

* hyplnk_EXAMPLE_REFCLK_USE_PLATCFG can be commented out and the specific
* value specified below.
*****************************************************************************/
#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG
//#define hyplnk_EXAMPLE_REFCLK_156p25
//#define hyplnk_EXAMPLE_REFCLK_250p00
//#define hyplnk_EXAMPLE_REFCLK_312p50

"

This is the output at the C6678 side:

"

[C66xx_0] Version #: 0x02000007; string HYPLNK LLD Revision: 02.00.00.07:Jul 30 2013:10:02:29
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Scheme = 1
BU = 0
Func = 0x0e90
RTL = 4
cust = 0
revMaj = 1
revMin = 1
Status register contents:
Raw = 0x00003004
swidthin = 0
swidthout = 0
serialHalt = 1
pllUnlock = 1
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 0
Link status register contents:
Raw = 0x00000000
txPlsReq = 0
txPlsAck = 0
txPmReq = 0
txRSync = 0
txPlsOK = 0
txPhyEn = 0
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 0
rxLSync = 0
rxPhyEn = 0
rxPhyPol = 0
Control register contents:
Raw = 0x00000000
intLocal = 0
statusIntEnable = 0
statusIntVec = 0
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
Control register contents:
Raw = 0x00000000
sglErrCor = 0
dblErrDet = 0
============== end registers before initialization ===========
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 1
Link status register contents:
Raw = 0xccf00cff
txPlsReq = 3
txPlsAck = 0
txPmReq = 3
txRSync = 0
txPlsOK = 0
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 15
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 1
sPend = 0
mPend = 1
link = 1
Link status register contents:
Raw = 0xfdf0bdf0
txPlsReq = 3
txPlsAck = 3
txPmReq = 3
txRSync = 0
txPlsOK = 1
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 2
rxPlsAck = 3
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 0
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0
=== this is not an optimized example ===
Link Speed is 4 * 6.25 Gbps
Passed 65536 tokens round trip (read+write through hyplnk) in 17490 Mcycles
Approximately 266876 cycles per round-trip
=== this is not an optimized example ===
Checking statistics
About to pass 65536 tokens; iteration = 1

"

I shall send you via David the crucial files. 
I can pinpoint the problem at the following setting:
#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG

When I change this to the 156MHz reference clock setting, the old behaviour comes back. So could you explain why this behaviour occurs? Thanks in advance!

Good to know it is working!

So, are you saying with 156.25 common reference clock: Hawking side set to 156.25 however the Shannon side has to be set 312.5 to work?

The log you sent is for Hawking I believe, because LLD is 02.00.00.07, not 01.00.00.xx. Did you use my pre-build for testing? It should has LLD Version #: 02.00.00.08.

So although worked, something messed up. Can you provide the working case log for both sides?

Regards, Eric

Hello Eric,

It is indeed strange regarding the clock configuration. Hereby the logs:

The 66AK2H12:

[C66xx_0] Version #: 0x02000007; string HYPLNK LLD Revision: 02.00.00.07:Jul 30 2013:10:02:29
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Scheme = 1
BU = 0
Func = 0x0e90
RTL = 4
cust = 0
revMaj = 1
revMin = 1
Status register contents:
Raw = 0x00003004
swidthin = 0
swidthout = 0
serialHalt = 1
pllUnlock = 1
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 0
Link status register contents:
Raw = 0x00000000
txPlsReq = 0
txPlsAck = 0
txPmReq = 0
txRSync = 0
txPlsOK = 0
txPhyEn = 0
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 0
rxLSync = 0
rxPhyEn = 0
rxPhyPol = 0
Control register contents:
Raw = 0x00000000
intLocal = 0
statusIntEnable = 0
statusIntVec = 0
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
Control register contents:
Raw = 0x00000000
sglErrCor = 0
dblErrDet = 0
============== end registers before initialization ===========
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 1
Link status register contents:
Raw = 0xccf00cf0
txPlsReq = 3
txPlsAck = 0
txPmReq = 3
txRSync = 0
txPlsOK = 0
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 0
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 1
sPend = 0
mPend = 1
link = 1
Link status register contents:
Raw = 0xfdf0bdf0
txPlsReq = 3
txPlsAck = 3
txPmReq = 3
txRSync = 0
txPlsOK = 1
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 2
rxPlsAck = 3
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 0
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0

The C6678:

[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Scheme = 1
BU = 0
Func = 0x0e90
RTL = 3
cust = 0
revMaj = 1
revMin = 0
Status register contents:
Raw = 0x00002004
swidthin = 0
swidthout = 0
serialHalt = 1
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 0
Link status register contents:
Raw = 0x00000000
txPlsReq = 0
txPlsAck = 0
txPmReq = 0
txRSync = 0
txPlsOK = 0
txPhyEn = 0
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 0
rxLSync = 0
rxPhyEn = 0
rxPhyPol = 0
Control register contents:
Raw = 0x00000001
intLocal = 0
statusIntEnable = 0
statusIntVec = 0
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 1
Control register contents:
Raw = 0x00000000
sglErrCor = 0
dblErrDet = 0
============== end registers before initialization ===========
Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x03470c1d; lock = 1
Waiting for other side to come up ( 1)
Waiting for other side to come up ( 2)
Waiting for other side to come up ( 3)
Waiting for other side to come up ( 4)
Waiting for other side to come up ( 5)
Waiting for other side to come up ( 6)
Waiting for other side to come up ( 7)
Waiting for other side to come up ( 8)
Waiting for other side to come up ( 9)
Waiting for other side to come up ( 10)
Waiting for other side to come up ( 11)
SERDES_STS (32 bits) contents: 0x02060c19; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 0
sPend = 1
mPend = 0
link = 1
Link status register contents:
Raw = 0xccf00cf0
txPlsReq = 3
txPlsAck = 0
txPmReq = 3
txRSync = 0
txPlsOK = 0
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 0
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Link seems stable
About to try to read remote registers
============== begin REMOTE registers after initialization ===========
Status register contents:
Raw = 0x0440000b
swidthin = 4
swidthout = 4
serialHalt = 0
pllUnlock = 0
rPend = 0
iFlow = 0
oFlow = 0
rError = 0
lError = 0
nfEmpty3 = 0
nfEmpty2 = 0
nfEmpty1 = 0
nfEmpty0 = 1
sPend = 0
mPend = 1
link = 1
Link status register contents:
Raw = 0xfdf0bdf0
txPlsReq = 3
txPlsAck = 3
txPmReq = 3
txRSync = 0
txPlsOK = 1
txPhyEn = 15
txFlowSts = 0
rxPlsReq = 2
rxPlsAck = 3
rxPmReq = 3
rxLSync = 0
rxPhyEn = 15
rxPhyPol = 0
Control register contents:
Raw = 0x00006200
intLocal = 1
statusIntEnable = 1
statusIntVec = 2
int2cfg = 0
serialStop = 0
iLoop = 0
reset = 0
============== end REMOTE registers after initialization ===========
Peripheral setup worked
About to read/write once
Single write test passed
About to pass 65536 tokens; iteration = 0
=== this is not an optimized example ===
Link Speed is 4 * 6.25 Gbps
Passed 65536 tokens round trip (read+write through hyplnk) in 17080 Mcycles
Approximately 260632 cycles per round-trip
=== this is not an optimized example ===
Checking statistics

I shall also try out your files.

Hello Eric,

I tested your generated out files at our platform. I got the same the results as before. Both sides are hanging and the debuggers stop function. 

Hereby the logs:

66AKH2H12:

[C66xx_0] Version #: 0x02000008; string HYPLNK LLD Revision: 02.00.00.08:Sep 25 2013:05:54:53
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cff
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers

C6678:

[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
SERDES_STS (32 bits) contents: 0x03060c19; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Precursors 1 Analysis: 0,0,0,0,0,0,0,0
Postcursors: 19 Analysis: 0,0,0,0,0,0,0,0
Link seems stable
About to try to read remote registers

For your working case,

C6678 side, PLL=0x00000228; RX=0x0046c485; TX=0x000cc305. The PLL showed this is Ref clock 312.5 and data rate 6.25 Gb. Is this 6.25 expected in your test?

What is the set-up at the Hawking side? The log from Hawking "PLL=0x00000250; RX=0x0046c485; TX=0x000cc305" is misleading (This is our software issue, not yours, sorry for this). This was printed out in hyplnkExampleSysSetup(), but the actual setting/config is inside hyplnkExamplePeriphSetup() ----->hyplnkExampleDefSerdesSetup(), where you have the refClock, linkRate and lane_rate.

Based on your working setup, can you add a print function to see what are actually used? And is possible the 156.25 ref clock supply to 6678 multipled somehow?

Regards, Eric

Hello Eric,

My intention is to get it up and running at 6.25 Gbaud and later on 12.5 Gbaud (if already supported by TI).

I have checked function at the Hawking site. It is indeed configured at 156.25MHz reference clock and 6.25 Gbaud line rate. 

I see also the following statement:

"

if (ref_clock == CSL_SERDES_REF_CLOCK_156p25M && rate == CSL_SERDES_LINK_RATE_6p25G)
CSL_HYPERLINK_156p25Mhz_6p25g_SerDes_laneConfigure(base_addr, lane_num);

"

So I can conclude that this is the only valid configuration supported with this example project? 

We don't have 156.25/12.5 support at this moment.

Regards, Eric