C6670 Bootloader: How to append a boot configuration table to a boot table?

Hi, Rahul

We try to modified our working dummy project with DDR config according to the example you attached. And after one day's try, we seem to get more understandings of how to config DDR using the DDR EMIF table. Somehow, we have some new question. We hope you can give us some help.

1)Here is part of "spiboot.map" file from your attached file.

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  DDR_CFG        008ffd20      00000180  00000178  00000008  RWIX
  L2MAGIC           008ffffc         00000004  00000000  00000004  RWIX
  DDR                   80000000   00002000  00000c5c  000013a4  RWIX

Do we need to modified the DDR_CONFIG origin address? We are using C6670. According to the <SPRUGY5B> Table 2-2, the DDR configuration table should be put in (0x8fffff - 0xd23f +0x740) = 0x8f3500.

2)Here is part of "spiboot.c" file from your attached file.

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
 BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
 BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
 BOOT_EMIF_ENABLE_SLSW_config6 | \
 BOOT_EMIF_ENABLE_SLSW_config7 | \
 BOOT_EMIF_ENABLE_SLSW_config8 | \
 BOOT_EMIF_ENABLE_SLSW_config9 | \
 BOOT_EMIF_ENABLE_SLSW_config10 | \
 BOOT_EMIF_ENABLE_SLSW_config18 | \
 BOOT_EMIF_ENABLE_SLSW_config19 | \
 BOOT_EMIF_ENABLE_SLSW_config20 | \
 BOOT_EMIF_ENABLE_SLSW_config22 | \
 BOOT_EMIF_ENABLE_SLSW_config12 | \
 BOOT_EMIF_ENABLE_SLSW_config23 | \
 BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
   
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */ --------------------------question 1>

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
   
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0  ----------------------question 2>
};

1>These three parts seem to take no effect, maybe I'm doing wrong, I hope you could point it out.

When I set this table to 0x8ffd20, we can test the DDR frequency is 66.667MHz whatever we changed these three parts, our input CLK is 66.667MHz.

When I set this table to 0x8f3500, we can test the DDR frequency is 10.08MHz whatever we changed these three parts, our input CLK is 10.08MHz.

This makes us so confuse to get further.

2>What do these 64 32-bit values mean? Do we have to modify these values from your attached?

3>We found some of the annotations in the "emif4cfg table" is with "dont care".Does it means these values can be anything and we don't have to care about them?

Looking forward to your reply cause your advice is very helpful.Thank you!

Karlphy

Hi, Rahul

With your help, we have work out the DDR configuration!Thank you! And now, we are facing the last step: Booting multicores. We hope that you can help us with an example or some advices. I have started a new post  and I gave you veryfied answer on this post. Here is the new post link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/289371.aspx

Thank you!

Karlphy

Hi, Rahul

I follow this post instead of opening a new post because the question we met has some relationship with this post. I hope you don't mind. 

We have finished booting the 4 cores, using a HelloWorld simple project. And we solved the address problem through changing the package and cmd file of the project. 

When we boot our own project, we can go into main() funtion. But when the code allocate the DDR memory, a hint was shown: "[C66xx_0] ti.sysbios.heaps.HeapMem: line 307: out of memory: handle=0x10869318, size=1030464
xdc.runtime.Error.raise: terminating execution" We guess there is something wrong with the heap.  The shown length is a bit larger than our definition. Something odd is that when we use the emulator to connect the DSP, it runs successfully and there is no error occured. Our gel file is similar to the 6670EVM gel file with some ddr configuration changes. We guess that there is something of the DDR config we have never noticed. 

Here is part of "tiboot.h" file from you attached "7080.SPIboot_ddr.zip"

/*******************************************************************************
* Emif4 (DDR3) configuration table
*******************************************************************************/
typedef struct bootEmif4Tbl_s {

UINT32 configSelect_msw; /* Bit map defining which registers to set */
UINT32 configSelect_slsw; /* Bit map defining which registers to set */
UINT32 configSelect_lsw; /* Bit map defining which registers to set */

UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;

UINT32 sdRamConfig; /* Controlled by bit 1 of configSelect_msw */
UINT32 sdRamConfig2; /* Bit 2 */
UINT32 sdRamRefreshCtl; /* Bit 3 */
UINT32 sdRamTiming1; /* Bit 4 */
UINT32 sdRamTiming2; /* Bit 5 */
UINT32 sdRamTiming3; /* Bit 6 */
UINT32 lpDdrNvmTiming; /* Bit 7 */
UINT32 powerManageCtl; /* Bit 8 */
UINT32 iODFTTestLogic; /* Bit 9 */
UINT32 performCountCfg; /* Bit 10 */
UINT32 performCountMstRegSel; /* Bit 11 */
UINT32 readIdleCtl; /* Bit 12 */
UINT32 sysVbusmIntEnSet; /* Bit 13 */
UINT32 sdRamOutImpdedCalCfg; /* Bit 14 */
UINT32 tempAlterCfg; /* Bit 15 */
UINT32 ddrPhyCtl1; /* Bit 16 */
UINT32 ddrPhyCtl2; /* Bit 17 */
UINT32 priClassSvceMap; /* Bit 18 */
UINT32 mstId2ClsSvce1Map; /* Bit 19 */
UINT32 mstId2ClsSvce2Map; /* Bit 20 */
UINT32 eccCtl; /* Bit 21 */
UINT32 eccRange1; /* Bit 22 */
UINT32 eccRange2; /* Bit 23 */
UINT32 rdWrtExcThresh; /* Bit 24 */

UINT32 chipConfig[64];

} BOOT_EMIF4_TBL_T;

Here is part of "toboot.h" file from 6670 bootloader source code("C6670_pg10_bootloader.zip")

/*******************************************************************************
* Emif4 (DDR3) configuration table
*******************************************************************************/
typedef struct bootEmif4Tbl_s {

UINT32 configSelect; /* Bit map defining which registers to set */

UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;

UINT32 sdRamConfig;
UINT32 sdRamConfig2;
UINT32 sdRamRefreshCtl;
UINT32 sdRamTiming1;
UINT32 sdRamTiming2;
UINT32 sdRamTiming3;
UINT32 lpDdrNvmTiming;
UINT32 powerManageCtl;
UINT32 iODFTTestLogic;
UINT32 performCountCfg;
UINT32 performCountMstRegSel;
UINT32 readIdleCtl;
UINT32 sysVbusmIntEnSet;
UINT32 sdRamOutImpdedCalCfg;
UINT32 tempAlterCfg;
UINT32 ddrPhyCtl1;
UINT32 ddrPhyCtl2;
UINT32 priClassSvceMap;
UINT32 mstId2ClsSvce1Map;
UINT32 mstId2ClsSvce2Map;
UINT32 eccCtl;
UINT32 eccRange1;
UINT32 eccRange2;
UINT32 rdWrtExcThresh;

} BOOT_EMIF4_TBL_T;

We can see there are something different between the two parts. We are using the 6670 bootloader version and it worked till now(DDR can be read and written correctly). Our question is: Should we config the UINT32 chipConfig[64] . part of DDR? If so, how to config? If not, how can we solved this heap problem? We guess there is something wrong with this part because the gel file has do some part of config in UINT32 chipConfig[64] . 

Another question: We know that before loading codes to L2 and DDR, we should config the PLL(using boot parameter table) and DDR(in this case, using emif4 config table). Is there anyting we should config before bootloading except for PLL and DDR? If so, how to do the conifg? 

Waiting for your reply, it's urgent. Thank you for you patience.

Karlphy

Hi Rahul

As the last reply by  Karlphy Fong , I dont think the exsample 7080.SPIboot_ddr.zip is for C6670.

Can you tell me how can I find the DDR_CONFIG address for C6670 and C6678? I can not find out the Table 2-2 in the last Bootloader User Guide (SPRUGY9C). Why is It removed?

Hi Karlphy,

Sorry for interrupting you.

Did you solve the DDR configuration problem?
I'm using C6670 and facing to the DDR configuration problem.
I made a DDR EMIF table as mentioned in this post, but DDR access is unstable.
Are there any additional setting for DDR3 during RBL boot?
I guess DDR3 Configuration Register need to be set during RBL boot,
but I don't know how to configurate the register.

If you have any information, can you please share with me?

best regards,
g.f.

YI Yin,

The DDR config table is being moved from bootloader user guide to the Data manual which is why it is removed. We plan to release the new data sheet soon which should reflect this change. In the mean time you can refer to the ROM code source provided here:

http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture

Regards,

Rahul

PS: Please start a new thread when a thread is closed or verified as it is easier to track

Hi gf,

If you are configuring the DDR to max speed please try to reduce the DDR speed and then re-initialize the DDR from the application code after performing DDR leveling. Currently DDR leveling is not supported in the ROM.

Regards,

Rahul

Hi Rahul,

Thank you for the reply.

Okay, I will reduce the DDR3 speed.
By the way, I have question about re-initializing DDR3.
Do you mean that we need to allocate application code in internal RAM
for re-initializing DDR3?

best regards,
g.f.

HI Karlphy Fong and G.F,

Can you please share how you did DDR3 configuration. I am trying with above steps but I am unable to boot the board.

Thank You,

Nithin