This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6657 L2 Type

Genius 5785 points

Hello,

There are two types of C66x L2 configuration, 0 wait-states and 2 × 128-bit banks, 1 wait-state and 4 × 128-bit banks. Which one is C6657? I can't find the description in data manual.

Regards,
Kazu

  • Hi Kazu,

    There are two types of C66x L2 configuration, 0 wait-states and 2 × 128-bit banks, 1 wait-state and 4 × 128-bit banks.

    Please provide the document reference for the above statement.

    The L2 memory configuration for the C6655/57 device is as follows:

    • Total memory is 1024KB (C6655)

    • Total memory is 2048KB (C6657)

    As per corepac UG -L2SRAM:

    The configuration features 3 wait states for L2SRAM, 8 x 128 bit banks which is made up of two physical banks with four sub-banks each.

    Thank you.

  • Hello Rajasekaran,

    Thank you for your reply. You can see the statement below.

    C66x Cache User Guide (SPRUGY8) -> P.58

    Regards,
    Kazu

  • Hi Kon

    I think that the document that you look at is more generic document. My understanding is that if there are four banks of memory, then an additional wait cycle is added for the additional control of the four banks, but my understanding is that C6678 as well as C6657 devices have the same L2 architecture, namely, two banks, 128bit each

    The C66 core user guide of 6657 (www.ti.com/.../technicaldocuments ) refer to www.ti.com/.../sprugw0c.pdf and in 4.2.1.3 you see the architecture of L2

    But the best way for you to measure the L2 delay is to disable cache, define two pointers, one into L1D and one into L2, and measure the time it takes to read a value from L1D and compare it to the time it takes to read from l2. I do not thibk that L2 gives you 0 wait-state read.
    For write though there are buffers that can mitigate the write delay.

    Does it make sense? If so, close the thread


    Ran
  • Hi Ran,
    Thank you for the clarification.