hi, all
im new to the timer. I want to use timers and generate 1KHz frequncy from GPIO pins like pwm Using timer IRQs form kernel space driver .
but the interrupt doesnot function and even the counter doesnot change. we are using dvsdk 4 with kernel linux-2.6.32.17-psp03.01.01.38
i have tried with 3timers but i get different value in the readonly register PID12 however:
LCD:PID12:0x0, EMUMGT 0x0 timer 1
LCD:PID12:0x44722a0b, EMUMGT 0x0 timer 3
LCD:PID12:0x10701, EMUMGT 0x0 timer 4
does it make sense that all of them are different ? i have seen that PID12 is just for timer0,1,2,4. since timer0 is used for the system clock, and timer2 canonly used for WDT,so i can only use timer1,3,4. am i correct ?
here is the code snippets:
00132: struct lcd_dev lcd_devices = {
00133: .fpd = 1,
00134: .period = 100,
00135: .base = IO_ADDRESS(DAVINCI_TIMER3_BASE),
00136: .cmp_off = 0,
00137: .cmp_irq = 0,
00138: .bottom_irq = IRQ_DM365_TINT6, /* 15 INT6 timer 1:2*/
00139: .top_irq = 22, /* 22 INT7 timer 3:4 */
00140: };
00032: #define DAVINCI_TIMER1_BASE (0x1c21800)
00033: #define DAVINCI_TIMER3_BASE (0x1c20800)
00034: #define DAVINCI_TIMER4_BASE (0x1c23800)
00035:
00036: #define DAVINCI_ARM_INTC_IO_BASE (IO_ADDRESS(0x01C48000))
00038: /* Timer register offsets */
00039: #define PID12 0x0
00040: #define TIM12 0x10
00041: #define TIM34 0x14
00042: #define PRD12 0x18
00043: #define PRD34 0x1c
00044: #define TCR 0x20
00045: #define TGCR 0x24
00046: #define WDTCR 0x28
00047: #define INTCTL_STAT 0x44
//...
00401: /***************************************
00402: * init the Clock
00403: ***************************************/
00404: timer_clk = clk_get(NULL, "timer3");
00405: BUG_ON(IS_ERR(timer_clk));
00406: clk_enable(timer_clk);
00407:
00408: /***************************************
00409: * init the registers
00410: ***************************************/
00411: debug("PID12:0x%x, EMUMGT 0x%x\n", __raw_readl(lcd_devices .base + PID12), __raw_readl(
00411: lcd_devices .base + 4));
00412:
00413: /* Disabled, Internal clock source */
00414: __raw_writel(0, lcd_devices .base + TCR);
00415:
00416: /* reset both timers, no pre-scaler for timer34 */
00417: __raw_writel(0, lcd_devices .base + TGCR);
00418:
00419: /* Set both timers to unchained 32-bit */
00420: tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
00421: __raw_writel(tgcr, lcd_devices .base + TGCR);
00422:
00423: /* Unreset timers */
00424: tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
00425: __raw_writel(tgcr, lcd_devices .base + TGCR);
00426:
00427: /* Init both counters to zero */
00428: __raw_writel(0, lcd_devices .base + TIM12);
00429: __raw_writel(0, lcd_devices .base + TIM34);
00430:
00431:
00432: /* period */
00433: __raw_writel(lcd_devices .period, lcd_devices .base + PRD12);
00434: /* first phase duration */
00435: __raw_writel(lcd_devices .fpd, lcd_devices .base + PRD34);
00436:
00437: /* only for time 34 : PSC34 = Prescaler : 1 : like no Prescaler */
00438: __raw_writel(1<<TGCR_PSC34_SHIFT, lcd_devices .base + TGCR);
00439:
00440: /***************************************
00441: * enable the timer
00442: ***************************************/
00443:
00444: /* ENAMODE12/ENAMODE34 = continuously */
00445: tgcr = TCR_ENAMODE_PERIODIC << 6;
00446: tgcr |= TCR_ENAMODE_PERIODIC << 22;
00447: __raw_writel(tgcr, lcd_devices .base + TCR); /* Enable it */
00448:
00449:
00450: /***************************************
00451: * init IRQs
00452: ***************************************/
00454: /* timer prescale counter */
00455: rv = request_irq(lcd_devices .top_irq, timer34_isr, IRQF_DISABLED, DEVICE_NAME, NULL);
00456: if(rv)
00457: {
00458: err("can't get assigned irq %i", lcd_devices .bottom_irq);
00459: goto dev_del;
00460: }
00461:
00462: /* timer counter */
00463: rv = request_irq(lcd_devices .bottom_irq, timer12_isr, IRQF_DISABLED, DEVICE_NAME, NULL);
00464: if(rv)
00465: {
00466: err("can't get assigned irq %i", lcd_devices .bottom_irq);
00467: goto dev_del;
00468: }
00469:
00470: /***************************************
00471: * enable the interrupt mask
00472: ***************************************/
00473: irq_enable(lcd_devices .top_irq);
00474: irq_enable(lcd_devices .bottom_irq);
00475:
00476: /***************************************
00477: * enable interrupt
00478: ***************************************/
00479: addr = lcd_devices .base + INTCTL_STAT;
00480: tgcr = __raw_readl(addr) | BIT(16) | BIT(0);
00481:
00482: __raw_writel(tgcr, addr);
the code source file is here. 5758.lcd-11.09.16.10.21.10.rar
did i miss anything?
any help will be appreciated.
Thinks in advance.
regards, mike
