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DM368 DDR2 access problem

g.f.
Guru 15520 points

Hi,

I have a few question about DM368 DDR2.

We are having a CPU exception problem caused by DDR2 write/read access
while doing audio encode process.
When reading 32bytes data from DDR2, the first 4byte data was not expected value.
The next 4 bytes was data which should be read first and after that
it keeps reading 4byte front of the appropriate data.

Is this DDR2 Read latency problem ?
So, do you think it might be solved by setting appropriate value to DDRPHYCR1 register?
Or is there any other factor to cause this problem like if DQGATE Length didn't match to
the "CK net plus the average length of the DQS0 and DQS1 nets"?

Another question is about DDR2 PBBPR(Peripheral Bus Burst Priority Register).
In DDR2 User's Guide page.53 "Note", it said that you must change the default value other than 0xFF.
What kind of value should I set to the PBBPR.PR_OLD_COUNT?

best regards,
g.f.

  • 0
    TI__Genius 9775 points

    Make sure you program a large enough CAS Latency on both the DDRPHY register as well as one of the timing registers.

    PBBPR is more of a performance register.  I don't anticipate this would cause a wrong read-back.

  • 0 in reply to Ivan Garcia
    Guru 15520 points

    Hi Ivan,

    Thank you for the response.

    Can I ask about READ_LATENCY bit field of DDRPHY register.

    The memory CAS Latency is 5 , and customer sets the READ_LATENCY to 7.
    But in TRM page.44 the value of READ_LATENCY is described as follow:
    **********************************************************
    The minimum (READ_LATENCY) value is CAS latency plus 1 and
    the maximum (READ_LATENCY) value isCAS latency plus 2
    (again, the (READ_LATENCY) field would be programmed to these values minus 1).
    ***********************************************************

    So, I think that the value of READ_LATENCY should be 5(min) or 6(max).
    Min: READ_LATENCY = CAS Latency + 1 - 1 = 5
    Max: READ_LATENCY = CAS Latency + 2 - 1 = 6
    Am I right?

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Mastermind 49091 points

      If you assume the round trip board delay is two DDR_CLK cycles, then you're right. Programing READ_LATENCY to 5 or 6 shall solve the issue.

      Thanks!

      Phil