Som question about DM368 (Performance & Power Consumption)

Hi,

We have got 1080P30 with capture on DM368 IPNC Reference Design. When i say 30 fps, i am talking from overall system perspective (with capture and encoding). With streaming turned on, we are at margin and at times see a little under 30fps (29.8-30) system performance. In all the use cases, codec still performs above 30fps.

Can you tell me whether you see 29.5 fps across VIDENC1_process function call or across the system level? Also, can you explain the DDR accesses in your capture flow? As you mentioned, changing ARM form 399 to 432 MHz did not improve codec performance, this adds to our theory that it is DDR that is causing the issue. So please help us understand your DDR accesses and any other DMA accesses that you are doing?

For power numbers, i will get back to you with more details.

Regards,

Anshuman

thank you Anshuman

More information is here

a. Video Encoding Path

    ISIF -> Resize A (1920x1080) -> YUV420 -> H.264 Encoding (8000 Kbps)

                 Resize B(352x240) -> YUV420 (not encoding, no more process)

                 (not use AEWB, Motion Detection, Not streaming)

b. Audio Path

   Audio External Codec -> I2S -> MBCSP -> Audio Codec(AAC or G..711)

c. Video Out Path (PreView)

  DMA Copy To Video Outbuffer -> Digital (YCbCr16) -> HDMI Trans

I just turn on A(Video Encoding Path, Other not used) -> 29.6~29.8 FPS (System Performance 29.6, Encoding 29.8)

More detail power information is here

DM368 36Mzh Xtal , Arm Core:371Mhz, DDR:680Mhz(340Mhz)

a. 1080P Encoding  video output

     DM368(1.35V):568mA

     DM368(1.8V) + DDR(1.8V):295mA

b. 1080P Encoding

     DM368(1.35V):575mA

     DM368(1.8V) + DDR(1.8V):228mA

c. 720P Encoding  video output

      DM368(1.35V):472mA

     DM368(1.8V) + DDR(1.8V):240mA

d. 720P Encoding

      DM368(1.35V):435mA

     DM368(1.8V) + DDR(1.8V):150mA

Sungil,

The power numbers that were measured look reasonable.  They are in the range of power consumption that I expect for DM368.

Regards,

-phil

Hi,

In the below encoding path, you have enabled RSZ B. What is it intended for? We do not add any extra resize option in our capture flow. I think if you disable RSZB, then i am sure you should be able to comfortably get encode performance of above 30 fps and system performance around 30fps.

Sungil Kim said:

a. Video Encoding Path

    ISIF -> Resize A (1920x1080) -> YUV420 -> H.264 Encoding (8000 Kbps)

                 Resize B(352x240) -> YUV420 (not encoding, no more process)

                 (not use AEWB, Motion Detection, Not streaming)

The RSZB output to DDR is unnecessary DDR bandwidth consumption.

For your display path, we have not evaluated how much would be the impact of extra DDR on codec, but i assume that the performance numbers you are seeing are reasonable. You are adding 1920x1080x1.5x30x3 Bytes/sec DDR read and write operations, which surely is a huge DDR load.

Regards,

Anshuman

PS: Please mark this post as verified if you think it has answered your question. Thanks.

I've tried speeding up our DM368 to run the DDR at 340MHz but the board locks when UBL loads the PLL and DDR parameters.  I feel that it's the DDR parameters that are at fault.  Could you post the DDR setup code in your UBL?

Thanks,

John A

Hi John

Here is  our code

Uint32 DEVICE_DDR2Init()
{
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);

    SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F;

    // Set bit CLRZ (bit 13)
    SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000;

    // Check VTP READY Status
    while( !(SYSTEM->VTPIOCR & 0x8000));    

    // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
    //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000;        

    // Set bit LOCK(bit7) and PWRSAVE (bit8)
    SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080;    

    // Powerdown VTP as it is locked (bit 6)
    // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
    SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040;

    // Wait for calibration to complete
    UTIL_waitLoop( 150 );

    // Set the DDR2 to synreset, then enable it again
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET);
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);

    DDR->DDRPHYCR = 0x000000C6;

    DDR->SDBCR = 0x00D34A32;        //Program SDRAM Bank Config Register
    DDR->SDBCR = 0x0053CA32;

    DDR->SDTIMR  =0x576D7D12;         //Program SDRAM Timing Control Register1
    DDR->SDTIMR2 =0x422EC742;         //Program SDRAM Timing Control Register2

    DDR->PBBPR = 0x000000FE;

    DDR->SDBCR = 0x08534832;         //Program SDRAM Bank Config Register

    DDR->SDRCR = 0xA5C;            //Program SDRAM Refresh Control Register     

    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET);
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);

    return E_PASS;
}

good luck

Thanks Sungil,

I did find some code for running the DDR at 340MHZ and got it working.  It's very close to what you posted. One thing that's interesting is the code for setting the SDBCR (SDCR in the documentation) is setting a reserved bit to 1 for apparently no reason.

So while your code shows...

DDR->SDBCR = 0x00D34A32

The code supplied would be...

DDR->SDBCR = 0x08D34A32

John A