Hi,
I'm troubleshooting an issue with a AM3874/TI8148 talking to a Broadcom gigabit PHY using RGMII. The processor can receive data at gigabit link speeds, and sends replies out the RGMII interface, yet the PHY fails to send this out to the magnetics. This leads me to question the internal delay for GTXCLK-to-TXD[3..0] signals on the EMAC for the processor.
The AM3874 datasheet mentions a "EMAC RGMII_ID_MODE_N register" (pg 222-223) that controls whether this internal delay is enabled or disabled; however I can't find any more information about this register.
Does somebody know what it's memory address is and have a description for each bit?
Thanks,
- Kyle