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RGMII_ID_MODE_N register on AM3874/TI8148?

Other Parts Discussed in Thread: AM3874

Hi,

I'm troubleshooting an issue with a AM3874/TI8148 talking to a Broadcom gigabit PHY using RGMII.  The processor can receive data at gigabit link speeds, and sends replies out the RGMII interface, yet the PHY fails to send this out to the magnetics.  This leads me to question the internal delay for GTXCLK-to-TXD[3..0] signals on the EMAC for the processor.

The AM3874 datasheet mentions a "EMAC RGMII_ID_MODE_N register" (pg 222-223) that controls whether this internal delay is enabled or disabled; however I can't find any more information about this register.

Does somebody know what it's memory address is and have a description for each bit?

Thanks,

- Kyle

  • Kyle

    RGMII internal delay can be controlled using GMII_SEL register. Its offset is 0x48140650. The description as follows.

    with regards

    Mugunthan V N

  • This was my issue, thank you very much.   After I updated the value to 0x112 and all is well on my end for RGMII0.

    For others interested, I updated u-boot which set this register in board_init().  The previous code was __raw_writel(0x30a,GMII_SEL);

  • Hi,

    I have another question, do you know if RGMIIx_ID_MODE affects the internal delay for RX and TX clocks?  It doesn't explain exactly, and I'm trying to understand why disabling the disabling the GTXCLK delay on the PHY didn't resolve the problem in the same manner.

    Thanks,

    - Kyle

  • Hi,

    We are using DM8148 processor on our board. We are using EMAC1 for our Ethernet interface . The data rate transfer happens only for 100Mbps.When we try setting our PC to 1000Mbps using mii-tool eth0 -r command and then do dhcp , auto negotiation happens and the speed will be reduced to 100Mbps automatically and the data transfer takes place. Same is the problem with 10Mbps. Our PC supports 10/100/1000Mbps speed.

    Please can someone help us on this?

    Thanks

    Prakash

  • Kyle Manna said:

    This was my issue, thank you very much.   After I updated the value to 0x112 and all is well on my end for RGMII0.

    For others interested, I updated u-boot which set this register in board_init().  The previous code was __raw_writel(0x30a,GMII_SEL);

    Hi Kyle

    I use BCM54610 in my 8147 project too.

    If the phy need to be disabled or enabled internal delay?

    Thank you.