UART4 Baud Rate Adjustment on DM8148

BenM

Hello,

I am using DM8148 with EZSDK 5.04.00.11. I am seeing that when i set the baud rate of UART4 that it actually sets it to a rate exactly 4x faster than baud rate. If set the serial port to B9600 the ARM I communicate fine when I set my PC to B38400. I am assuming that there is a clock divider/multiplier setting that needs to be set but i have been unable to change it. I tried clk_set_rate() but it was unable to change it (I am assuming because other devices are also using the clock at that point). Is there a way to simply change the multiplier/divider so that the baud rate is accurate?

Thanks,

-Ben

over 13 years ago

0 SEUNGSIK KWAK over 13 years ago

Intellectual 590 points

Hi,

I have had same issue on DM8148 with EZSDK 5.04.00.11. The DM8148 on our custom board needs to communicate with MSP430 using UART4 but the received data on MSP430 is unreadable - like 0xff. It looks like baud rate issue even though 115200, 38400 and 9600 are set and tested on both side. I doubt about source clock for UART4 and it has 192MHz instead of 48MHz which is used for UART0/1/2. The source clock can be changed via "McBSP_UART_CLKSRC Register" - p518 DM8148 TRM. Also, the default clock configuration is in p803, Table 4-7. ROM Code Default Clock Settings, DM8148.

Once the clock source changes to sysclk10, 9600 and 115200 baud rate work without issue. For me, I modify board-ti8148evm.c as below.

static void __init ti8148_evm_init(void)
{

...

// set UART4 source clock to sysclk10 - 48MHz such as UART0/1/2/3 have
{
void __iomem *addr = ioremap((unsigned long)(0x481c5000 + 0x2d8), 4*1024/*4K*/);
if (!addr) {
panic("Set to sysclk10 for UART4...");
}

__raw_writel((1 << 5), addr); /* sysclk10 as a reference clock */
}

ti814x_evm_i2c_init();
ti81xx_register_mcasp(0, &ti8148_evm_snd_data);

...

I hope that it helps you out.

Regards,

0 Jeppe Ledet-Pedersen over 13 years ago in reply to SEUNGSIK KWAK

Prodigy 180 points

I had the same issue and fixed it using:

__raw_writel((1 << 5), TI814X_PLL_CMGC_MCBSP_UART_CLKSRC);

But I'm not sure if this is the right approach or if I should use a function from the clk tree framework? Can someone from TI clarify this?

Thanks.

-Jeppe

Processors

Processors forum

UART4 Baud Rate Adjustment on DM8148