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DM8148 allowed clock frequencies

Chris P
Intellectual 505 points

Hi,

I'm working through an RF interference issue on my board (based on the Appro INPC) and I'd like to change the MPU clock frequency. Am I limited to the 50/100/120/166 OPP options (300, 600, 720, 1000 MHz, respectively) or can I set the PLL to whatever I wish?

I will be using the ISS/VPSS/DSP/Links architecture, so are there restrictions and/or interactions that I need to be aware of?

Do I also have to consider the DDR3 clock rates?

Changing the cpu frequency in U-boot (IPNC 2.8) is trivial but seems significantly more complicated in Linux. Can I just add the frequencies I want to the OPP table or is there much more to the story?

Thanks,
Chris

  • 0
    TI__Expert 6655 points

    Hi Chris,

    You can refer these sections in DataSheet to know the limits

    1) 7.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)

    2) 7.4.6.3 PLL Frequency Limits

    3) 7.4.8 Module Clocks

    And refer this wiki section to configure PLLs in kernel

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_Clock_Framework_User_Guide#Usage

    Regards

    AnilKumar

    Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

  • 0 in reply to Anil
    Intellectual 505 points

    Hi Anil,

    Thanks, but I have read those sections of the specification and the answer to my original question still isn't clear to me. The spec lists maximum & minimum clock rates but doesn't speak directly to the values between.

    So, for example, say I set MODENA_N = 1, MODENA_M = 0x3b, MODENA_M2 = 1 for a final frequency of 590 MHz (instead of the OPP100 rate of 600 MHz). Could I still set the DSP/HDVICP2/etc to OPP100 and expect the system to work correctly?

    Or is the Cortex A8 limited to one of 300/600/720/1000 MHz and I shouldn't attempt to use a different setting?

    Thanks,
    Chris

  • 0 in reply to Chris P
    TI__Expert 6655 points

    Hi Chris,

    Output frequency of the PLL should meet the limitations mentioned in the "2.5 DPLLS & 2.6 DPLLLJ" sections. By meeting those constraints we can set the frequency as required.

    As coming to your specific question we can set MODENA output frequency as 590MHz and maintain DSP/HDVICP2/etc to OPP100 provided there is not interdependency between the module clocks. From DM8148 clocking scheme I can say DSP/HDVICP are from independent PLLs.

    OPP is a combination of function(voltage, frequency) so we have maintain voltage according to OPP100 if we reduce frequency. While increasing the frequency we have to maintain next higher OPP voltage.

    Regards

    AnilKumar

    Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!