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How to make McBSP work at DSP core of DM8148?

Other Parts Discussed in Thread: OMAP-L138

I met some problem while trying to make McBSP work at DSP core of DM8148.

Hope somebody can help.

Detail information:

I am using TMS320DM8148BCYE0 v2.1 on the board. McBSP is connected with external IC to transmit/receive data with SSI protocol.

External IC is the SSI master, CLKR/FSR, CLKX/FSX are provided by external IC. McBSP is controlled at C674x core.

McBSP Clock initialization:

    writel(0x03, CM_SYSCLK20_CLKSEL);
    while(readl(CM_SYSCLK20_CLKSEL) != 0x3);

    writel(0x0, MCBSP_UART_CLKSRC);  // choose RPCM output
    while(readl(MCBSP_UART_CLKSRC) != 0x0);

    writel(0x0, CM_AUDIOCLK_MCBSP_CLKSEL);  // choose sysclk20
    while(readl(CM_AUDIOCLK_MCBSP_CLKSEL) != 0x0);

    writel(0x2, CM_ALWON_L3_SLOW_CLKSTCTRL);                // Enable L3 clock
    while(((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & (0x01<<12))>>12)!=0x1); // Confirm L3 clock enable

    writel(0x2, CM_ALWON_MCBSP_CLKCTRL);                    // enable mcbsp clock
    while(readl(CM_ALWON_MCBSP_CLKCTRL) != 0x2);

McBSP registers are configured to work as slave. Other configuration are ported from OMAP-L138 McBSP driver.

Observation:

    Rx Clock and Rx FSYNC can be captured, but RRDY is always 0, DMA and interrupt all can't work.

It looks that McBSP block isn't working at all.

Is there any sample code for DM8148 McBSP driver?

Most of my code are ported from OMAP-L138, is there any special difference need take care?

Thanks a lot!

  • It is found that FRST and GRST need be set to 1 even McBSP is working as slave mode, means CLKX and CLKR are driven by

    external device. The behaviour is different from that of OMAP-L138.

    Can anybody explain this?

  • From Latest TRM:

    17.2.8 Programming Model
    17.2.8.1 McBSP Initialization Procedure
    The serial port initialization procedure is as follows:
    1. Clear SPCR1_REG[0] register RRST bit, SPCR2_REG[7] register FRST bit, and SPCR2_REG[0]
    register XRST bit to 0. If coming out of a global reset, this step is not required.
    2. While the serial port is in the reset state, program only the McBSP configuration registers (not the data
    registers) as required.
    3. Wait for two clock cycles. This ensures proper internal synchronization
    4. Set SPCR1_REG[0] register RRST bit and SPCR2_REG[0] register XRST bit to 1 to enable the serial
    port. Make sure that as you set these reset bits, you do not modify any of the other bits in
    SPCR1_REG and SPCR2_REG registers. Otherwise, you would change the configuration set in step
    2.
    5. Set up data acquisition as required (such as writing to DXR_REG register).
    6. Set SPCR2_REG[7] register FRST bit to 1 if internally generated frame synchronization is required.
    7. Wait for two clock cycles for the receiver and transmitter to become active.