DM8147 based EP does not enumerate in some x86 PC based RC

Stephen,

When using a non-DM81xx RC (i.e. x86 RC), the below application note should be considered:

http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_PCIe_Clocking_Schemes

Also the below links are useful for debugging:

http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#How_can_I_enable_debugging_the_PCI.2FPCIe_enumeration_and_configuration.3F

http://processors.wiki.ti.com/index.php/TI81XX_PSP_U-Boot_PCIe_Boot_User_Guide#Connecting_EVM_to_host_PC

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Driver_User_Guide

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Boot_Driver_User_Guide

Regards,
Pavel

Hi Pavel

I note the following errata:

Advisory 3.0.66 PCI Express (PCIe): PCIe Boot Fails When Connected to Some PCs

Revisions Affected:3.0 and earlier

Details:

The ROM code cannot handle hot-reset or disable-link packets. It has been observed on
some motherboards on some slots, that the PC BIOS issues hot-reset or disable-link
transactions on the PCIe bus. When the device sees these transactions, the PCIe
controller gets reset automatically.
This reset causes the PCIe controller to lose the configuration that was programmed by
ROM and, as a result, the PCIe boot does not complete. This issue is seen only when
interfacing with some PCs. It is not seen when one device acting as root complex tries to
boot another device acting as endpoint.

Workaround:

There is no PCIe boot workaround that ensures operation for all PC motherboards and
slots. To avoid this issue, PCIe boot from a PC slot should be avoided. Booting from SPI
flash will allow S/W detection of hot-reset transactions on the PCIe bus and
reconfiguration of the PCIe controller.

Does TI have u-boot or linux driver code that shows how to apply the workaround?.

thanks

Steve

Steve,

Stephen Turner said:

To avoid this issue, PCIe boot from a PC slot should be avoided. Booting from SPI
flash will allow S/W detection of hot-reset transactions on the PCIe bus and
reconfiguration of the PCIe controller.

Does TI have u-boot or linux driver code that shows how to apply the workaround?.

I think you just need to boot from SPI flash (not from PCIe) then use the EP driver.

For boot from SPI flash, refer to the below wiki pages:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_Flashing_Tools_Guide#Burning_images_to_SPI_Flash_.28using_CCS.29

http://processors.wiki.ti.com/index.php/DM814x_AM387x_PSP_Flashing_Tools_Guide#Burning_images_to_SPI_Flash_.28using_CCS.29

http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#U-Boot_SPI_Support

For PCIe EP:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Driver_User_Guide

BR
Pavel

Hi Pavel

We are booting u-boot from SPI flash.  U-boot sets up the PCIe interface and then loads DSP firmware from the PC.

While waiting for the PC to load firmware, on some PCs, we are seeing the PCIe interface transition into the HOT_RESET state.  This seems to cause a board reset, thus causing u-boot to run again.  The 2nd time around however, the PCIe PLL never locks and u-boot hangs.

I'm assuming the HOT_RESET state is valid, however I don't think u-boot is handling it correctly?

-steve

Stephen,

Stephen Turner said:

U-boot sets up the PCIe interface and then loads DSP firmware from the PC.

By DSP firmware, do you mean the dm81xx_c6xdsp_debug.xe674 file?

Can you try loading it not from the u-boot, but from the rootfs, when the linux kernel is up and running?

BR
Pavel

Hi Pavel

We have written our own c674x DSP code to provide audio transfer to/from the PCIe bus and processing, so, no we do not use the TI DSP code.

We do not use Linux in this product.  u-boot is ONLY used to init the PCIe interface and download DSP firmware from the host (x86 PC).  The ARM is then put into idle mode.

Most PCs seem to work fine.  However there are a few that are exhibiting the problem of issuing the HOT_RESET.

thanks

Hi Pavel

Any more info on this?.  I need u-boot code to support the  following highlighted statement:

Workaround:

There is no PCIe boot workaround that ensures operation for all PC motherboards and
slots. To avoid this issue, PCIe boot from a PC slot should be avoided. Booting from SPI
flash will allow S/W detection of hot-reset transactions on the PCIe bus and
reconfiguration of the PCIe controller.

thanks

Stephen,

We have some PCIe u-boot patches, which looks related:

ti814x: pcie: Add PCIe boot support
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=68292ba92892de12224a39e31143a24d6098d92c

pcie: Add support for 64-bit configuration
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=bccbf7ca00fa7f9cf8f1b65df0374a659cd8c3d6

ti81xx: pcie: fix build warning
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=5c7b6c802080b94f6c7ba0c6b7454b88c371069f

ti81xx: pcie: Add support for PCIe boot for TI816X in SPI mode
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=6105b554443355f4e2356b107d5a5f9eb4a2f09e

ti81xx: pcie: Add support for  PCIe boot mode for TI813X
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=d00b969ea47651393313bb436b1fcc571bd183d6

ti81xx: pcie: Remove warnings
http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=f9423f668c011d238db61cbf39f44b978e6b746e

Are you aware of these patches? Are they in help?

Regards,
Pavel

The below wiki pages and links seems to be also related:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_U-Boot_PCIe_Boot_User_Guide#Tuning.2FChanging_options

http://processors.wiki.ti.com/index.php/DM81xx_AM38xx_PCI_Express_Root_Complex_Driver_User_Guide#Troubleshooting

http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#How_can_I_initialize_PCIe_module_on_DM816x_to_be_used_as_PCIe_Endpoint_without_using_any_of_the_PCIe_Boot_mode.3F

http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#what.E2.80.99s_the_difference_between_pcie_boot_and_SPI_pcie_boot_support.3F

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/260354.aspx

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/237375.aspx

DM814x TRM, section 4.8.5 PCIe Boot Procedure and section 19.2.12 PCIe Power Management


Regards,
Pavel

Pavel,

The patched updates did not resolve the issue.

The issue is stated in the DM814x Errata, Advisory 3.0.66 PCI Express (PCIe): PCIe Boot Fails When Connected to Some PCs.

Is there any work being done on our end to find a work-around? In this application it is not an option to boot from SPI flash.

Hi David

Our product is actually booting from SPI flash. 

It is booting u-boot, which then does the PCIe init that the DM814x ROM would normally do.  I'm hoping there are additional patches to u-boot that will allow "S/W detecttion of hot-reset transactions on the PCIe bus" as described in the Workaround to Advisory 3.0.66

thanks

Steve

Stephen, David,

These are all the u-boot patches that we have:

http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

Stephen Turner said:

I'm hoping there are additional patches to u-boot that will allow "S/W detecttion of hot-reset transactions on the PCIe bus" as described in the Workaround to Advisory 3.0.66

I do not find such u-boot PCIe patch.

I will check again with the PCIe team, if they have something to share.

Regards,
Pavel

Hi Pavel

Wondering if you have any updates on this.  Maybe the PCIe team is working on a different processors PCIe u-boot code, that may be more robust?.  How about the Keystone II chips?

thanks

Steve

Steve,

Stephen Turner said:

Maybe the PCIe team is working on a different processors PCIe u-boot code, that may be more robust?

I will check with the PCIe team, if they have something to share.

Stephen Turner said:

How about the Keystone II chips?

Meanwhile you can ask/post in the corresponding forums. You can check in the OMAP5/Vayu forum and Keystone forum.

Regards,
Pavel

Steve,

This is the feedback from the OMAP5/Vayu PCIe team:

We don't have PCIe support in u-boot.

In the current kernel code PCIe controller is configured only once by the driver.

BR
Pavel